Matheus Almeida 8e7aa4be58 [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions. ... This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-26 16:09:43 +00:00
..
AArch64
ARM	Teach llvm-readobj to print human friendly description of reserved sections.	2014-03-24 05:00:34 +00:00
AsmParser
COFF
Disassembler	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
ELF	Correctly detect if a symbol uses a reserved section index or not.	2014-03-26 00:16:43 +00:00
MachO	Fix crashes when assembler directives are used that are not	2014-03-25 00:05:50 +00:00
Markup
Mips	[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.	2014-03-26 16:09:43 +00:00
PowerPC	[PowerPC] Generate little-endian object files	2014-03-24 18:16:09 +00:00
Sparc
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
X86