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f7f22a64df
When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the bitwidth of the second operands to both ands match before comparing the negation of the values. Split the check of the value of the second operands to the ands. Move the cast and variable declaration slightly higher to make it slightly easier to follow. Bug-Id: 16700 Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
1.0 KiB
LLVM
33 lines
1.0 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
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; ModuleID = 'bugpoint-reduced-simplified.bc'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7--linux-gnueabi"
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; CHECK-LABEL: function
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define void @function() {
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; CHECK: cmp r0, #0
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; CHECK: bxne lr
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; CHECK: vmov.i32 q8, #0xff0000
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entry:
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br i1 undef, label %vector.body, label %for.end
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; CHECK: vld1.32 {d18, d19}, [r0]
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; CHECK: vand q10, q9, q8
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; CHECK: vbic.i16 q9, #0xff
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; CHECK: vorr q9, q9, q10
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; CHECK: vst1.32 {d18, d19}, [r0]
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vector.body:
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%wide.load = load <4 x i32>* undef, align 4
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%0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936>
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%1 = sub <4 x i32> %wide.load, zeroinitializer
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%2 = and <4 x i32> %1, <i32 16711680, i32 16711680, i32 16711680, i32 16711680>
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%3 = or <4 x i32> undef, %0
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%4 = or <4 x i32> %3, %2
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store <4 x i32> %4, <4 x i32>* undef, align 4
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br label %vector.body
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for.end:
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ret void
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}
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