llvm-6502/test/CodeGen/ARM/ifconv-regmask.ll
Matthias Braun 4e54f41d6c ARM: do not add a regmask for TAILJUMPs
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 16:52:54 +00:00

36 lines
997 B
LLVM

; RUN: llc < %s -mtriple=thumbv7s-apple-ios6.0.0 -verify-machineinstrs
%union.opcode = type { i32 }
@opcode = external global %union.opcode, align 4
; Function Attrs: nounwind ssp
define i32 @sfu() {
entry:
%bf.load = load i32* getelementptr inbounds (%union.opcode* @opcode, i32 0, i32 0), align 4
%bf.lshr = lshr i32 %bf.load, 26
%bf.clear = and i32 %bf.lshr, 7
switch i32 %bf.clear, label %return [
i32 0, label %sw.bb
i32 1, label %sw.bb1
]
sw.bb: ; preds = %entry
%call = tail call i32 @func0()
br label %return
sw.bb1: ; preds = %entry
%call2 = tail call i32 @func1()
br label %return
return: ; preds = %sw.bb1, %sw.bb, %entry
%retval.0 = phi i32 [ %call2, %sw.bb1 ], [ %call, %sw.bb ], [ -1, %entry ]
ret i32 %retval.0
}
; Function Attrs: nounwind ssp
declare i32 @func0()
; Function Attrs: nounwind ssp
declare i32 @func1()