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https://github.com/c64scene-ar/llvm-6502.git
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t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
1098 lines
34 KiB
C++
1098 lines
34 KiB
C++
//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMSubtarget.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmParser.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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using namespace llvm;
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// The shift types for register controlled shifts in arm memory addressing
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enum ShiftType {
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Lsl,
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Lsr,
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Asr,
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Ror,
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Rrx
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};
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namespace {
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class ARMOperand;
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class ARMAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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TargetMachine &TM;
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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int TryParseRegister();
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bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemoryOffsetReg(bool &Negative,
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bool &OffsetRegShifted,
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enum ShiftType &ShiftType,
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const MCExpr *&ShiftAmount,
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const MCExpr *&Offset,
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bool &OffsetIsReg,
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int &OffsetRegNum,
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SMLoc &E);
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bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool ParseDirectiveThumb(SMLoc L);
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bool ParseDirectiveThumbFunc(SMLoc L);
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bool ParseDirectiveCode(SMLoc L);
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bool ParseDirectiveSyntax(SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out);
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/// @name Auto-generated Match Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "ARMGenAsmMatcher.inc"
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/// }
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public:
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ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
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: TargetAsmParser(T), Parser(_Parser), TM(_TM) {
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(
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&TM.getSubtarget<ARMSubtarget>()));
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}
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virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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};
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} // end anonymous namespace
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namespace {
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/// ARMOperand - Instances of this class represent a parsed ARM machine
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/// instruction.
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class ARMOperand : public MCParsedAsmOperand {
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enum KindTy {
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CondCode,
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Immediate,
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Memory,
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Register,
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RegisterList,
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DPRRegisterList,
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SPRRegisterList,
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Token
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} Kind;
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SMLoc StartLoc, EndLoc;
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SmallVector<unsigned, 8> Registers;
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union {
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struct {
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ARMCC::CondCodes Val;
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} CC;
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNum;
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} Reg;
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struct {
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const MCExpr *Val;
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} Imm;
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// This is for all forms of ARM address expressions
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struct {
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unsigned BaseRegNum;
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unsigned OffsetRegNum; // used when OffsetIsReg is true
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const MCExpr *Offset; // used when OffsetIsReg is false
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const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
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enum ShiftType ShiftType; // used when OffsetRegShifted is true
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unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
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unsigned Preindexed : 1;
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unsigned Postindexed : 1;
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unsigned OffsetIsReg : 1;
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unsigned Negative : 1; // only used when OffsetIsReg is true
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unsigned Writeback : 1;
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} Mem;
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};
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ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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public:
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ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
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Kind = o.Kind;
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StartLoc = o.StartLoc;
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EndLoc = o.EndLoc;
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switch (Kind) {
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case CondCode:
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CC = o.CC;
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break;
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case Token:
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Tok = o.Tok;
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break;
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case Register:
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Reg = o.Reg;
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break;
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case RegisterList:
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case DPRRegisterList:
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case SPRRegisterList:
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Registers = o.Registers;
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break;
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case Immediate:
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Imm = o.Imm;
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break;
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case Memory:
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Mem = o.Mem;
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break;
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}
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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ARMCC::CondCodes getCondCode() const {
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assert(Kind == CondCode && "Invalid access!");
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return CC.Val;
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNum;
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}
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const SmallVectorImpl<unsigned> &getRegList() const {
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assert((Kind == RegisterList || Kind == DPRRegisterList ||
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Kind == SPRRegisterList) && "Invalid access!");
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return Registers;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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bool isCondCode() const { return Kind == CondCode; }
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bool isImm() const { return Kind == Immediate; }
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bool isReg() const { return Kind == Register; }
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bool isRegList() const { return Kind == RegisterList; }
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bool isDPRRegList() const { return Kind == DPRRegisterList; }
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bool isSPRRegList() const { return Kind == SPRRegisterList; }
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bool isToken() const { return Kind == Token; }
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bool isMemory() const { return Kind == Memory; }
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bool isMemMode5() const {
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if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
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Mem.Writeback || Mem.Negative)
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return false;
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// If there is an offset expression, make sure it's valid.
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if (!Mem.Offset) return true;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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if (!CE) return false;
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// The offset must be a multiple of 4 in the range 0-1020.
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int64_t Value = CE->getValue();
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return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
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}
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bool isMemModeThumb() const {
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if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
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return false;
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if (!Mem.Offset) return true;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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if (!CE) return false;
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// The offset must be a multiple of 4 in the range 0-124.
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uint64_t Value = CE->getValue();
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return ((Value & 0x3) == 0 && Value <= 124);
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible. Null MCExpr = 0.
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if (Expr == 0)
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Inst.addOperand(MCOperand::CreateImm(0));
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else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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void addCondCodeOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
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// FIXME: What belongs here?
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Inst.addOperand(MCOperand::CreateReg(0));
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addRegListOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const SmallVectorImpl<unsigned> &RegList = getRegList();
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for (SmallVectorImpl<unsigned>::const_iterator
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I = RegList.begin(), E = RegList.end(); I != E; ++I)
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Inst.addOperand(MCOperand::CreateReg(*I));
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}
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void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
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addRegListOperands(Inst, N);
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}
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void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
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addRegListOperands(Inst, N);
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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void addMemMode5Operands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && isMemMode5() && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
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assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
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// FIXME: #-0 is encoded differently than #0. Does the parser preserve
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// the difference?
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if (Mem.Offset) {
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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assert(CE && "Non-constant mode 5 offset operand!");
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// The MCInst offset operand doesn't include the low two bits (like
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// the instruction encoding).
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int64_t Offset = CE->getValue() / 4;
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if (Offset >= 0)
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
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Offset)));
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else
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Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
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-Offset)));
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} else {
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Inst.addOperand(MCOperand::CreateImm(0));
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}
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}
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void addMemModeThumbOperands(MCInst &Inst, unsigned N) const {
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assert(N == 3 && isMemModeThumb() && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
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if (Mem.Offset) {
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
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assert(CE && "Non-constant mode offset operand!");
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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Inst.addOperand(MCOperand::CreateReg(0));
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} else {
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Inst.addOperand(MCOperand::CreateImm(0));
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Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
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}
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}
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virtual void dump(raw_ostream &OS) const;
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static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
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ARMOperand *Op = new ARMOperand(CondCode);
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Op->CC.Val = CC;
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
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ARMOperand *Op = new ARMOperand(Token);
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Op->Tok.Data = Str.data();
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Op->Tok.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(Register);
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Op->Reg.RegNum = RegNum;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static ARMOperand *
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CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
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SMLoc StartLoc, SMLoc EndLoc) {
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KindTy Kind = RegisterList;
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if (ARM::DPRRegClass.contains(Regs.front().first))
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Kind = DPRRegisterList;
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else if (ARM::SPRRegClass.contains(Regs.front().first))
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Kind = SPRRegisterList;
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ARMOperand *Op = new ARMOperand(Kind);
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for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
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I = Regs.begin(), E = Regs.end(); I != E; ++I)
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Op->Registers.push_back(I->first);
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array_pod_sort(Op->Registers.begin(), Op->Registers.end());
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Op->StartLoc = StartLoc;
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Op->EndLoc = EndLoc;
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return Op;
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}
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static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(Immediate);
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
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const MCExpr *Offset, unsigned OffsetRegNum,
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bool OffsetRegShifted, enum ShiftType ShiftType,
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const MCExpr *ShiftAmount, bool Preindexed,
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bool Postindexed, bool Negative, bool Writeback,
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SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(Memory);
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Op->Mem.BaseRegNum = BaseRegNum;
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Op->Mem.OffsetIsReg = OffsetIsReg;
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Op->Mem.Offset = Offset;
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Op->Mem.OffsetRegNum = OffsetRegNum;
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Op->Mem.OffsetRegShifted = OffsetRegShifted;
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Op->Mem.ShiftType = ShiftType;
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Op->Mem.ShiftAmount = ShiftAmount;
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Op->Mem.Preindexed = Preindexed;
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Op->Mem.Postindexed = Postindexed;
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Op->Mem.Negative = Negative;
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Op->Mem.Writeback = Writeback;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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};
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} // end anonymous namespace.
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void ARMOperand::dump(raw_ostream &OS) const {
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switch (Kind) {
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case CondCode:
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OS << ARMCondCodeToString(getCondCode());
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break;
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case Immediate:
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getImm()->print(OS);
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break;
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case Memory:
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OS << "<memory>";
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break;
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case Register:
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OS << "<register " << getReg() << ">";
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break;
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case RegisterList:
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case DPRRegisterList:
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case SPRRegisterList: {
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OS << "<register_list ";
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const SmallVectorImpl<unsigned> &RegList = getRegList();
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for (SmallVectorImpl<unsigned>::const_iterator
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I = RegList.begin(), E = RegList.end(); I != E; ) {
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OS << *I;
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if (++I < E) OS << ", ";
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}
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OS << ">";
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break;
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}
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case Token:
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OS << "'" << getToken() << "'";
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break;
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}
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}
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/// @name Auto-generated Match Functions
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/// {
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static unsigned MatchRegisterName(StringRef Name);
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/// }
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/// Try to parse a register name. The token must be an Identifier when called,
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/// and if it is a register name the token is eaten and the register number is
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/// returned. Otherwise return -1.
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///
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int ARMAsmParser::TryParseRegister() {
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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unsigned RegNum = MatchRegisterName(Tok.getString());
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if (RegNum == 0)
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return -1;
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Parser.Lex(); // Eat identifier token.
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return RegNum;
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}
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/// Try to parse a register name. The token must be an Identifier when called.
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/// If it's a register, an AsmOperand is created. Another AsmOperand is created
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/// if there is a "writeback". 'true' if it's not a register.
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///
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/// TODO this is likely to change to allow different register types and or to
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/// parse for a specific register type.
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bool ARMAsmParser::
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TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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int RegNo = TryParseRegister();
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if (RegNo == -1)
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return true;
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Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
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const AsmToken &ExclaimTok = Parser.getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
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ExclaimTok.getLoc()));
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Parser.Lex(); // Eat exclaim token
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}
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return false;
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}
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/// Parse a register list, return it if successful else return null. The first
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/// token must be a '{' when called.
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bool ARMAsmParser::
|
|
ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
assert(Parser.getTok().is(AsmToken::LCurly) &&
|
|
"Token is not a Left Curly Brace");
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
|
|
// Read the rest of the registers in the list.
|
|
unsigned PrevRegNum = 0;
|
|
SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
|
|
|
|
do {
|
|
bool IsRange = Parser.getTok().is(AsmToken::Minus);
|
|
Parser.Lex(); // Eat non-identifier token.
|
|
|
|
const AsmToken &RegTok = Parser.getTok();
|
|
SMLoc RegLoc = RegTok.getLoc();
|
|
if (RegTok.isNot(AsmToken::Identifier)) {
|
|
Error(RegLoc, "register expected");
|
|
return true;
|
|
}
|
|
|
|
int RegNum = TryParseRegister();
|
|
if (RegNum == -1) {
|
|
Error(RegLoc, "register expected");
|
|
return true;
|
|
}
|
|
|
|
if (IsRange) {
|
|
int Reg = PrevRegNum;
|
|
do {
|
|
++Reg;
|
|
Registers.push_back(std::make_pair(Reg, RegLoc));
|
|
} while (Reg != RegNum);
|
|
} else {
|
|
Registers.push_back(std::make_pair(RegNum, RegLoc));
|
|
}
|
|
|
|
PrevRegNum = RegNum;
|
|
} while (Parser.getTok().is(AsmToken::Comma) ||
|
|
Parser.getTok().is(AsmToken::Minus));
|
|
|
|
// Process the right curly brace of the list.
|
|
const AsmToken &RCurlyTok = Parser.getTok();
|
|
if (RCurlyTok.isNot(AsmToken::RCurly)) {
|
|
Error(RCurlyTok.getLoc(), "'}' expected");
|
|
return true;
|
|
}
|
|
|
|
SMLoc E = RCurlyTok.getLoc();
|
|
Parser.Lex(); // Eat right curly brace token.
|
|
|
|
// Verify the register list.
|
|
SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
|
|
RI = Registers.begin(), RE = Registers.end();
|
|
|
|
DenseMap<unsigned, bool> RegMap;
|
|
RegMap[RI->first] = true;
|
|
|
|
unsigned HighRegNum = RI->first;
|
|
bool EmittedWarning = false;
|
|
|
|
for (++RI; RI != RE; ++RI) {
|
|
const std::pair<unsigned, SMLoc> &RegInfo = *RI;
|
|
unsigned Reg = RegInfo.first;
|
|
|
|
if (RegMap[Reg]) {
|
|
Error(RegInfo.second, "register duplicated in register list");
|
|
return true;
|
|
}
|
|
|
|
if (!EmittedWarning && Reg < HighRegNum)
|
|
Warning(RegInfo.second,
|
|
"register not in ascending order in register list");
|
|
|
|
RegMap[Reg] = true;
|
|
HighRegNum = std::max(Reg, HighRegNum);
|
|
}
|
|
|
|
Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
|
|
return false;
|
|
}
|
|
|
|
/// Parse an ARM memory expression, return false if successful else return true
|
|
/// or an error. The first token must be a '[' when called.
|
|
///
|
|
/// TODO Only preindexing and postindexing addressing are started, unindexed
|
|
/// with option, etc are still to do.
|
|
bool ARMAsmParser::
|
|
ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
SMLoc S, E;
|
|
assert(Parser.getTok().is(AsmToken::LBrac) &&
|
|
"Token is not a Left Bracket");
|
|
S = Parser.getTok().getLoc();
|
|
Parser.Lex(); // Eat left bracket token.
|
|
|
|
const AsmToken &BaseRegTok = Parser.getTok();
|
|
if (BaseRegTok.isNot(AsmToken::Identifier)) {
|
|
Error(BaseRegTok.getLoc(), "register expected");
|
|
return true;
|
|
}
|
|
int BaseRegNum = TryParseRegister();
|
|
if (BaseRegNum == -1) {
|
|
Error(BaseRegTok.getLoc(), "register expected");
|
|
return true;
|
|
}
|
|
|
|
bool Preindexed = false;
|
|
bool Postindexed = false;
|
|
bool OffsetIsReg = false;
|
|
bool Negative = false;
|
|
bool Writeback = false;
|
|
|
|
// First look for preindexed address forms, that is after the "[Rn" we now
|
|
// have to see if the next token is a comma.
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.is(AsmToken::Comma)) {
|
|
Preindexed = true;
|
|
Parser.Lex(); // Eat comma token.
|
|
int OffsetRegNum;
|
|
bool OffsetRegShifted;
|
|
enum ShiftType ShiftType;
|
|
const MCExpr *ShiftAmount = 0;
|
|
const MCExpr *Offset = 0;
|
|
if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
|
|
Offset, OffsetIsReg, OffsetRegNum, E))
|
|
return true;
|
|
const AsmToken &RBracTok = Parser.getTok();
|
|
if (RBracTok.isNot(AsmToken::RBrac)) {
|
|
Error(RBracTok.getLoc(), "']' expected");
|
|
return true;
|
|
}
|
|
E = RBracTok.getLoc();
|
|
Parser.Lex(); // Eat right bracket token.
|
|
|
|
|
|
const AsmToken &ExclaimTok = Parser.getTok();
|
|
ARMOperand *WBOp = 0;
|
|
if (ExclaimTok.is(AsmToken::Exclaim)) {
|
|
WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
|
|
ExclaimTok.getLoc());
|
|
Writeback = true;
|
|
Parser.Lex(); // Eat exclaim token
|
|
}
|
|
|
|
Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
|
|
OffsetRegNum, OffsetRegShifted,
|
|
ShiftType, ShiftAmount, Preindexed,
|
|
Postindexed, Negative, Writeback,
|
|
S, E));
|
|
if (WBOp)
|
|
Operands.push_back(WBOp);
|
|
|
|
return false;
|
|
}
|
|
// The "[Rn" we have so far was not followed by a comma.
|
|
else if (Tok.is(AsmToken::RBrac)) {
|
|
// If there's anything other than the right brace, this is a post indexing
|
|
// addressing form.
|
|
E = Tok.getLoc();
|
|
Parser.Lex(); // Eat right bracket token.
|
|
|
|
int OffsetRegNum = 0;
|
|
bool OffsetRegShifted = false;
|
|
enum ShiftType ShiftType = Lsl;
|
|
const MCExpr *ShiftAmount = 0;
|
|
const MCExpr *Offset = 0;
|
|
|
|
const AsmToken &NextTok = Parser.getTok();
|
|
|
|
if (NextTok.isNot(AsmToken::EndOfStatement)) {
|
|
Postindexed = true;
|
|
Writeback = true;
|
|
|
|
if (NextTok.isNot(AsmToken::Comma)) {
|
|
Error(NextTok.getLoc(), "',' expected");
|
|
return true;
|
|
}
|
|
|
|
Parser.Lex(); // Eat comma token.
|
|
|
|
if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
|
|
ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
|
|
E))
|
|
return true;
|
|
}
|
|
|
|
Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
|
|
OffsetRegNum, OffsetRegShifted,
|
|
ShiftType, ShiftAmount, Preindexed,
|
|
Postindexed, Negative, Writeback,
|
|
S, E));
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
|
|
/// we will parse the following (were +/- means that a plus or minus is
|
|
/// optional):
|
|
/// +/-Rm
|
|
/// +/-Rm, shift
|
|
/// #offset
|
|
/// we return false on success or an error otherwise.
|
|
bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
|
|
bool &OffsetRegShifted,
|
|
enum ShiftType &ShiftType,
|
|
const MCExpr *&ShiftAmount,
|
|
const MCExpr *&Offset,
|
|
bool &OffsetIsReg,
|
|
int &OffsetRegNum,
|
|
SMLoc &E) {
|
|
Negative = false;
|
|
OffsetRegShifted = false;
|
|
OffsetIsReg = false;
|
|
OffsetRegNum = -1;
|
|
const AsmToken &NextTok = Parser.getTok();
|
|
E = NextTok.getLoc();
|
|
if (NextTok.is(AsmToken::Plus))
|
|
Parser.Lex(); // Eat plus token.
|
|
else if (NextTok.is(AsmToken::Minus)) {
|
|
Negative = true;
|
|
Parser.Lex(); // Eat minus token
|
|
}
|
|
// See if there is a register following the "[Rn," or "[Rn]," we have so far.
|
|
const AsmToken &OffsetRegTok = Parser.getTok();
|
|
if (OffsetRegTok.is(AsmToken::Identifier)) {
|
|
SMLoc CurLoc = OffsetRegTok.getLoc();
|
|
OffsetRegNum = TryParseRegister();
|
|
if (OffsetRegNum != -1) {
|
|
OffsetIsReg = true;
|
|
E = CurLoc;
|
|
}
|
|
}
|
|
|
|
// If we parsed a register as the offset then there can be a shift after that.
|
|
if (OffsetRegNum != -1) {
|
|
// Look for a comma then a shift
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat comma token.
|
|
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (ParseShift(ShiftType, ShiftAmount, E))
|
|
return Error(Tok.getLoc(), "shift expected");
|
|
OffsetRegShifted = true;
|
|
}
|
|
}
|
|
else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
|
|
// Look for #offset following the "[Rn," or "[Rn],"
|
|
const AsmToken &HashTok = Parser.getTok();
|
|
if (HashTok.isNot(AsmToken::Hash))
|
|
return Error(HashTok.getLoc(), "'#' expected");
|
|
|
|
Parser.Lex(); // Eat hash token.
|
|
|
|
if (getParser().ParseExpression(Offset))
|
|
return true;
|
|
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// ParseShift as one of these two:
|
|
/// ( lsl | lsr | asr | ror ) , # shift_amount
|
|
/// rrx
|
|
/// and returns true if it parses a shift otherwise it returns false.
|
|
bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
|
|
SMLoc &E) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Identifier))
|
|
return true;
|
|
StringRef ShiftName = Tok.getString();
|
|
if (ShiftName == "lsl" || ShiftName == "LSL")
|
|
St = Lsl;
|
|
else if (ShiftName == "lsr" || ShiftName == "LSR")
|
|
St = Lsr;
|
|
else if (ShiftName == "asr" || ShiftName == "ASR")
|
|
St = Asr;
|
|
else if (ShiftName == "ror" || ShiftName == "ROR")
|
|
St = Ror;
|
|
else if (ShiftName == "rrx" || ShiftName == "RRX")
|
|
St = Rrx;
|
|
else
|
|
return true;
|
|
Parser.Lex(); // Eat shift type token.
|
|
|
|
// Rrx stands alone.
|
|
if (St == Rrx)
|
|
return false;
|
|
|
|
// Otherwise, there must be a '#' and a shift amount.
|
|
const AsmToken &HashTok = Parser.getTok();
|
|
if (HashTok.isNot(AsmToken::Hash))
|
|
return Error(HashTok.getLoc(), "'#' expected");
|
|
Parser.Lex(); // Eat hash token.
|
|
|
|
if (getParser().ParseExpression(ShiftAmount))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Parse a arm instruction operand. For now this parses the operand regardless
|
|
/// of the mnemonic.
|
|
bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands){
|
|
SMLoc S, E;
|
|
switch (getLexer().getKind()) {
|
|
default:
|
|
Error(Parser.getTok().getLoc(), "unexpected token in operand");
|
|
return true;
|
|
case AsmToken::Identifier: {
|
|
if (!TryParseRegisterWithWriteBack(Operands))
|
|
return false;
|
|
|
|
// This was not a register so parse other operands that start with an
|
|
// identifier (like labels) as expressions and create them as immediates.
|
|
const MCExpr *IdVal;
|
|
S = Parser.getTok().getLoc();
|
|
if (getParser().ParseExpression(IdVal))
|
|
return true;
|
|
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
|
|
return false;
|
|
}
|
|
case AsmToken::LBrac:
|
|
return ParseMemory(Operands);
|
|
case AsmToken::LCurly:
|
|
return ParseRegisterList(Operands);
|
|
case AsmToken::Hash:
|
|
// #42 -> immediate.
|
|
// TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
|
|
S = Parser.getTok().getLoc();
|
|
Parser.Lex();
|
|
const MCExpr *ImmVal;
|
|
if (getParser().ParseExpression(ImmVal))
|
|
return true;
|
|
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/// Parse an arm instruction mnemonic followed by its operands.
|
|
bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
// Create the leading tokens for the mnemonic, split by '.' characters.
|
|
size_t Start = 0, Next = Name.find('.');
|
|
StringRef Head = Name.slice(Start, Next);
|
|
|
|
// Determine the predicate, if any.
|
|
//
|
|
// FIXME: We need a way to check whether a prefix supports predication,
|
|
// otherwise we will end up with an ambiguity for instructions that happen to
|
|
// end with a predicate name.
|
|
// FIXME: Likewise, some arithmetic instructions have an 's' prefix which
|
|
// indicates to update the condition codes. Those instructions have an
|
|
// additional immediate operand which encodes the prefix as reg0 or CPSR.
|
|
// Just checking for a suffix of 's' definitely creates ambiguities; e.g,
|
|
// the SMMLS instruction.
|
|
unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
|
|
.Case("eq", ARMCC::EQ)
|
|
.Case("ne", ARMCC::NE)
|
|
.Case("hs", ARMCC::HS)
|
|
.Case("lo", ARMCC::LO)
|
|
.Case("mi", ARMCC::MI)
|
|
.Case("pl", ARMCC::PL)
|
|
.Case("vs", ARMCC::VS)
|
|
.Case("vc", ARMCC::VC)
|
|
.Case("hi", ARMCC::HI)
|
|
.Case("ls", ARMCC::LS)
|
|
.Case("ge", ARMCC::GE)
|
|
.Case("lt", ARMCC::LT)
|
|
.Case("gt", ARMCC::GT)
|
|
.Case("le", ARMCC::LE)
|
|
.Case("al", ARMCC::AL)
|
|
.Default(~0U);
|
|
|
|
if (CC == ~0U ||
|
|
(CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
|
|
CC = ARMCC::AL;
|
|
} else {
|
|
Head = Head.slice(0, Head.size() - 2);
|
|
}
|
|
|
|
Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
|
|
|
|
if (Head != "trap")
|
|
// FIXME: Should only add this operand for predicated instructions
|
|
Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC),
|
|
NameLoc));
|
|
|
|
// Add the remaining tokens in the mnemonic.
|
|
while (Next != StringRef::npos) {
|
|
Start = Next;
|
|
Next = Name.find('.', Start + 1);
|
|
Head = Name.slice(Start, Next);
|
|
|
|
Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
|
|
}
|
|
|
|
// Read the remaining operands.
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
// Read the first operand.
|
|
if (ParseOperand(Operands)) {
|
|
Parser.EatToEndOfStatement();
|
|
return true;
|
|
}
|
|
|
|
while (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
// Parse and remember the operand.
|
|
if (ParseOperand(Operands)) {
|
|
Parser.EatToEndOfStatement();
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
Parser.EatToEndOfStatement();
|
|
return TokError("unexpected token in argument list");
|
|
}
|
|
|
|
Parser.Lex(); // Consume the EndOfStatement
|
|
return false;
|
|
}
|
|
|
|
bool ARMAsmParser::
|
|
MatchAndEmitInstruction(SMLoc IDLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
MCStreamer &Out) {
|
|
MCInst Inst;
|
|
unsigned ErrorInfo;
|
|
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
|
|
case Match_Success:
|
|
Out.EmitInstruction(Inst);
|
|
return false;
|
|
case Match_MissingFeature:
|
|
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
|
|
return true;
|
|
case Match_InvalidOperand: {
|
|
SMLoc ErrorLoc = IDLoc;
|
|
if (ErrorInfo != ~0U) {
|
|
if (ErrorInfo >= Operands.size())
|
|
return Error(IDLoc, "too few operands for instruction");
|
|
|
|
ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
|
|
if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
|
|
}
|
|
|
|
return Error(ErrorLoc, "invalid operand for instruction");
|
|
}
|
|
case Match_MnemonicFail:
|
|
return Error(IDLoc, "unrecognized instruction mnemonic");
|
|
}
|
|
|
|
llvm_unreachable("Implement any new match types added!");
|
|
return true;
|
|
}
|
|
|
|
/// ParseDirective parses the arm specific directives
|
|
bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
if (IDVal == ".word")
|
|
return ParseDirectiveWord(4, DirectiveID.getLoc());
|
|
else if (IDVal == ".thumb")
|
|
return ParseDirectiveThumb(DirectiveID.getLoc());
|
|
else if (IDVal == ".thumb_func")
|
|
return ParseDirectiveThumbFunc(DirectiveID.getLoc());
|
|
else if (IDVal == ".code")
|
|
return ParseDirectiveCode(DirectiveID.getLoc());
|
|
else if (IDVal == ".syntax")
|
|
return ParseDirectiveSyntax(DirectiveID.getLoc());
|
|
return true;
|
|
}
|
|
|
|
/// ParseDirectiveWord
|
|
/// ::= .word [ expression (, expression)* ]
|
|
bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
for (;;) {
|
|
const MCExpr *Value;
|
|
if (getParser().ParseExpression(Value))
|
|
return true;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
// FIXME: Improve diagnostic.
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveThumb
|
|
/// ::= .thumb
|
|
bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// TODO: set thumb mode
|
|
// TODO: tell the MC streamer the mode
|
|
// getParser().getStreamer().Emit???();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveThumbFunc
|
|
/// ::= .thumbfunc symbol_name
|
|
bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
|
|
return Error(L, "unexpected token in .thumb_func directive");
|
|
StringRef Name = Tok.getString();
|
|
Parser.Lex(); // Consume the identifier token.
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// Mark symbol as a thumb symbol.
|
|
MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
|
|
getParser().getStreamer().EmitThumbFunc(Func);
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveSyntax
|
|
/// ::= .syntax unified | divided
|
|
bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Identifier))
|
|
return Error(L, "unexpected token in .syntax directive");
|
|
StringRef Mode = Tok.getString();
|
|
if (Mode == "unified" || Mode == "UNIFIED")
|
|
Parser.Lex();
|
|
else if (Mode == "divided" || Mode == "DIVIDED")
|
|
Parser.Lex();
|
|
else
|
|
return Error(L, "unrecognized syntax mode in .syntax directive");
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// TODO tell the MC streamer the mode
|
|
// getParser().getStreamer().Emit???();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveCode
|
|
/// ::= .code 16 | 32
|
|
bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Integer))
|
|
return Error(L, "unexpected token in .code directive");
|
|
int64_t Val = Parser.getTok().getIntVal();
|
|
if (Val == 16)
|
|
Parser.Lex();
|
|
else if (Val == 32)
|
|
Parser.Lex();
|
|
else
|
|
return Error(L, "invalid operand to .code directive");
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
if (Val == 16)
|
|
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
|
|
else
|
|
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
|
|
|
|
return false;
|
|
}
|
|
|
|
extern "C" void LLVMInitializeARMAsmLexer();
|
|
|
|
/// Force static initialization.
|
|
extern "C" void LLVMInitializeARMAsmParser() {
|
|
RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
|
|
RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
|
|
LLVMInitializeARMAsmLexer();
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "ARMGenAsmMatcher.inc"
|