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https://github.com/c64scene-ar/llvm-6502.git
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1243922fc1
This pass was conservative in that it always reserved the FP to enable dynamic stack realignment, which allowed the RA to use aligned spills for vector registers. This happens even when spills were not necessary. The RA has since been improved to use unaligned spills when necessary. The new behavior is to realign the stack if the frame pointer was already reserved for some other reason, but don't reserve the frame pointer just because a function contains vector virtual registers. Part of rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168627 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
5.5 KiB
LLVM
130 lines
5.5 KiB
LLVM
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X32 %s
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; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X32 %s
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; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=WIN64 %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X64 %s
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declare <16 x float> @func_float16_ptr(<16 x float>, <16 x float> *)
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declare <16 x float> @func_float16(<16 x float>, <16 x float>)
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declare i32 @func_int(i32, i32)
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; WIN64: testf16_inp
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; WIN64: vaddps {{.*}}, {{%ymm[0-1]}}
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; WIN64: vaddps {{.*}}, {{%ymm[0-1]}}
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; WIN64: leaq {{.*}}(%rsp), %rcx
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; WIN64: call
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; WIN64: ret
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; X32: testf16_inp
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; X32: movl %eax, (%esp)
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; X32: vaddps {{.*}}, {{%ymm[0-1]}}
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; X32: vaddps {{.*}}, {{%ymm[0-1]}}
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; X32: call
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; X32: ret
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; X64: testf16_inp
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; X64: vaddps {{.*}}, {{%ymm[0-1]}}
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; X64: vaddps {{.*}}, {{%ymm[0-1]}}
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; X64: leaq {{.*}}(%rsp), %rdi
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; X64: call
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; X64: ret
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;test calling conventions - input parameters
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define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
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%y = alloca <16 x float>, align 16
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%x = fadd <16 x float> %a, %b
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%1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
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%2 = load <16 x float>* %y, align 16
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%3 = fadd <16 x float> %2, %1
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ret <16 x float> %3
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}
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;test calling conventions - preserved registers
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; preserved ymm6-ymm15
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; WIN64: testf16_regs
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; WIN64: call
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; WIN64: vaddps {{%ymm[6-7]}}, %ymm0, %ymm0
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; WIN64: vaddps {{%ymm[6-7]}}, %ymm1, %ymm1
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; WIN64: ret
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; preserved ymm8-ymm15
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; X64: testf16_regs
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; X64: call
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; X64: vaddps {{%ymm[8-9]}}, %ymm0, %ymm0
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; X64: vaddps {{%ymm[8-9]}}, %ymm1, %ymm1
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; X64: ret
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define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
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%y = alloca <16 x float>, align 16
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%x = fadd <16 x float> %a, %b
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%1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
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%2 = load <16 x float>* %y, align 16
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%3 = fadd <16 x float> %1, %b
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%4 = fadd <16 x float> %2, %3
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ret <16 x float> %4
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}
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; test calling conventions - prolog and epilog
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
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; WIN64: call
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill
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; X64: call
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload
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define intel_ocl_bicc <16 x float> @test_prolog_epilog(<16 x float> %a, <16 x float> %b) nounwind {
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%c = call <16 x float> @func_float16(<16 x float> %a, <16 x float> %b)
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ret <16 x float> %c
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}
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; test functions with integer parameters
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; pass parameters on stack for 32-bit platform
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; X32: movl {{.*}}, 4(%esp)
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; X32: movl {{.*}}, (%esp)
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; X32: call
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; X32: addl {{.*}}, %eax
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; pass parameters in registers for 64-bit platform
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; X64: leal {{.*}}, %edi
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; X64: movl {{.*}}, %esi
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; X64: call
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; X64: addl {{.*}}, %eax
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define i32 @test_int(i32 %a, i32 %b) nounwind {
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%c1 = add i32 %a, %b
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%c2 = call intel_ocl_bicc i32 @func_int(i32 %c1, i32 %a)
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%c = add i32 %c2, %b
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ret i32 %c
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}
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