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c98092e28d
The ELF object writer will take advantage of that in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234950 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.7 KiB
C++
79 lines
2.7 KiB
C++
//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Mips specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
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#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class StringRef;
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class Target;
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class raw_ostream;
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class raw_pwrite_stream;
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extern Target TheMipsTarget;
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extern Target TheMipselTarget;
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extern Target TheMips64Target;
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extern Target TheMips64elTarget;
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MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU);
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MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
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bool IsLittleEndian, bool Is64Bit);
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namespace MIPS_MC {
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StringRef selectMipsCPU(StringRef TT, StringRef CPU);
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}
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} // End llvm namespace
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// Defines symbolic names for Mips registers. This defines a mapping from
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// register name to register number.
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#define GET_REGINFO_ENUM
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#include "MipsGenRegisterInfo.inc"
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// Defines symbolic names for the Mips instructions.
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#define GET_INSTRINFO_ENUM
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#include "MipsGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "MipsGenSubtargetInfo.inc"
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#endif
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