mirror of
https://github.com/c64scene-ar/llvm-6502.git
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47622e3721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
172 lines
5.6 KiB
TableGen
172 lines
5.6 KiB
TableGen
//===- AlphaRegisterInfo.td - The Alpha Register File ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Alpha register set.
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//
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//===----------------------------------------------------------------------===//
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class AlphaReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "Alpha";
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}
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// We identify all our registers with a 5-bit ID, for consistency's sake.
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// GPR - One of the 32 32-bit general-purpose registers
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class GPR<bits<5> num, string n> : AlphaReg<n> {
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let Num = num;
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}
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// FPR - One of the 32 64-bit floating-point registers
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class FPR<bits<5> num, string n> : AlphaReg<n> {
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let Num = num;
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}
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//#define FP $15
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//#define RA $26
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//#define PV $27
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//#define GP $29
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//#define SP $30
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// General-purpose registers
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def R0 : GPR< 0, "$0">, DwarfRegNum<0>;
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def R1 : GPR< 1, "$1">, DwarfRegNum<1>;
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def R2 : GPR< 2, "$2">, DwarfRegNum<2>;
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def R3 : GPR< 3, "$3">, DwarfRegNum<3>;
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def R4 : GPR< 4, "$4">, DwarfRegNum<4>;
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def R5 : GPR< 5, "$5">, DwarfRegNum<5>;
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def R6 : GPR< 6, "$6">, DwarfRegNum<6>;
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def R7 : GPR< 7, "$7">, DwarfRegNum<7>;
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def R8 : GPR< 8, "$8">, DwarfRegNum<8>;
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def R9 : GPR< 9, "$9">, DwarfRegNum<9>;
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def R10 : GPR<10, "$10">, DwarfRegNum<10>;
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def R11 : GPR<11, "$11">, DwarfRegNum<11>;
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def R12 : GPR<12, "$12">, DwarfRegNum<12>;
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def R13 : GPR<13, "$13">, DwarfRegNum<13>;
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def R14 : GPR<14, "$14">, DwarfRegNum<14>;
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def R15 : GPR<15, "$15">, DwarfRegNum<15>;
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def R16 : GPR<16, "$16">, DwarfRegNum<16>;
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def R17 : GPR<17, "$17">, DwarfRegNum<17>;
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def R18 : GPR<18, "$18">, DwarfRegNum<18>;
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def R19 : GPR<19, "$19">, DwarfRegNum<19>;
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def R20 : GPR<20, "$20">, DwarfRegNum<20>;
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def R21 : GPR<21, "$21">, DwarfRegNum<21>;
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def R22 : GPR<22, "$22">, DwarfRegNum<22>;
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def R23 : GPR<23, "$23">, DwarfRegNum<23>;
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def R24 : GPR<24, "$24">, DwarfRegNum<24>;
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def R25 : GPR<25, "$25">, DwarfRegNum<25>;
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def R26 : GPR<26, "$26">, DwarfRegNum<26>;
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def R27 : GPR<27, "$27">, DwarfRegNum<27>;
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def R28 : GPR<28, "$28">, DwarfRegNum<28>;
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def R29 : GPR<29, "$29">, DwarfRegNum<29>;
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def R30 : GPR<30, "$30">, DwarfRegNum<30>;
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def R31 : GPR<31, "$31">, DwarfRegNum<31>;
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// Floating-point registers
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def F0 : FPR< 0, "$f0">, DwarfRegNum<33>;
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def F1 : FPR< 1, "$f1">, DwarfRegNum<34>;
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def F2 : FPR< 2, "$f2">, DwarfRegNum<35>;
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def F3 : FPR< 3, "$f3">, DwarfRegNum<36>;
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def F4 : FPR< 4, "$f4">, DwarfRegNum<37>;
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def F5 : FPR< 5, "$f5">, DwarfRegNum<38>;
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def F6 : FPR< 6, "$f6">, DwarfRegNum<39>;
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def F7 : FPR< 7, "$f7">, DwarfRegNum<40>;
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def F8 : FPR< 8, "$f8">, DwarfRegNum<41>;
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def F9 : FPR< 9, "$f9">, DwarfRegNum<42>;
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def F10 : FPR<10, "$f10">, DwarfRegNum<43>;
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def F11 : FPR<11, "$f11">, DwarfRegNum<44>;
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def F12 : FPR<12, "$f12">, DwarfRegNum<45>;
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def F13 : FPR<13, "$f13">, DwarfRegNum<46>;
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def F14 : FPR<14, "$f14">, DwarfRegNum<47>;
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def F15 : FPR<15, "$f15">, DwarfRegNum<48>;
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def F16 : FPR<16, "$f16">, DwarfRegNum<49>;
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def F17 : FPR<17, "$f17">, DwarfRegNum<50>;
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def F18 : FPR<18, "$f18">, DwarfRegNum<51>;
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def F19 : FPR<19, "$f19">, DwarfRegNum<52>;
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def F20 : FPR<20, "$f20">, DwarfRegNum<53>;
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def F21 : FPR<21, "$f21">, DwarfRegNum<54>;
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def F22 : FPR<22, "$f22">, DwarfRegNum<55>;
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def F23 : FPR<23, "$f23">, DwarfRegNum<56>;
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def F24 : FPR<24, "$f24">, DwarfRegNum<57>;
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def F25 : FPR<25, "$f25">, DwarfRegNum<58>;
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def F26 : FPR<26, "$f26">, DwarfRegNum<59>;
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def F27 : FPR<27, "$f27">, DwarfRegNum<60>;
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def F28 : FPR<28, "$f28">, DwarfRegNum<61>;
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def F29 : FPR<29, "$f29">, DwarfRegNum<62>;
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def F30 : FPR<30, "$f30">, DwarfRegNum<63>;
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def F31 : FPR<31, "$f31">, DwarfRegNum<64>;
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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// //#define GP $29
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// //#define SP $30
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// $28 is undefined after any and all calls
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/// Register classes
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def GPRC : RegisterClass<"Alpha", [i64], 64,
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// Volatile
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[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
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R23, R24, R25, R28,
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//Special meaning, but volatile
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R27, //procedure address
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R26, //return address
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R29, //global offset table address
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// Non-volatile
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R9, R10, R11, R12, R13, R14,
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// Don't allocate 15, 30, 31
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R15, R30, R31 ]> //zero
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{
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GPRCClass::iterator
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GPRCClass::allocation_order_end(MachineFunction &MF) const {
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return end()-3;
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}
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}];
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}
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def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1,
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F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
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// Saved:
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F2, F3, F4, F5, F6, F7, F8, F9,
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F31 ]> //zero
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{
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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F4RCClass::iterator
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F4RCClass::allocation_order_end(MachineFunction &MF) const {
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return end()-1;
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}
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}];
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}
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def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1,
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F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
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// Saved:
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F2, F3, F4, F5, F6, F7, F8, F9,
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F31 ]> //zero
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{
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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F8RCClass::iterator
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F8RCClass::allocation_order_end(MachineFunction &MF) const {
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return end()-1;
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}
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}];
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}
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