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2d4fa8faac
Preliminary support for division. It's gross because you have to initialize the "Y" register, which is the top 32 bits of the thing you're dividing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12732 91177308-0d34-0410-b5e6-96231b3b80d8
380 lines
14 KiB
C++
380 lines
14 KiB
C++
//===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a simple peephole instruction selector for the V8 target
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8InstrInfo.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicLowering.h"
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#include "llvm/Pass.h"
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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#include "llvm/Support/InstVisitor.h"
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#include "llvm/Support/CFG.h"
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using namespace llvm;
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namespace {
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struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
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TargetMachine &TM;
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
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// MBBMap - Mapping between LLVM BB -> Machine BB
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std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
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V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
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/// runOnFunction - Top level implementation of instruction selection for
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/// the entire function.
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///
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bool runOnFunction(Function &Fn);
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virtual const char *getPassName() const {
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return "SparcV8 Simple Instruction Selection";
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}
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/// visitBasicBlock - This method is called when we are visiting a new basic
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/// block. This simply creates a new MachineBasicBlock to emit code into
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/// and adds it to the current MachineFunction. Subsequent visit* for
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/// instructions will be invoked for all instructions in the basic block.
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///
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void visitBasicBlock(BasicBlock &LLVM_BB) {
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BB = MBBMap[&LLVM_BB];
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}
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void visitBinaryOperator(BinaryOperator &I);
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void visitCallInst(CallInst &I);
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void visitReturnInst(ReturnInst &RI);
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void visitInstruction(Instruction &I) {
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std::cerr << "Unhandled instruction: " << I;
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abort();
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}
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/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
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/// function, lowering any calls to unknown intrinsic functions into the
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/// equivalent LLVM code.
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void LowerUnknownIntrinsicFunctionCalls(Function &F);
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void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R);
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/// makeAnotherReg - This method returns the next register number we haven't
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/// yet used.
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///
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/// Long values are handled somewhat specially. They are always allocated
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/// as pairs of 32 bit integer values. The register number returned is the
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/// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
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/// of the long value.
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///
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unsigned makeAnotherReg(const Type *Ty) {
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assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
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"Current target doesn't have SparcV8 reg info??");
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const SparcV8RegisterInfo *MRI =
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static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
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if (Ty == Type::LongTy || Ty == Type::ULongTy) {
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const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
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// Create the lower part
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F->getSSARegMap()->createVirtualRegister(RC);
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// Create the upper part.
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return F->getSSARegMap()->createVirtualRegister(RC)-1;
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}
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// Add the mapping of regnumber => reg class to MachineFunction
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const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
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return F->getSSARegMap()->createVirtualRegister(RC);
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}
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unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
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unsigned getReg(Value *V) {
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// Just append to the end of the current bb.
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MachineBasicBlock::iterator It = BB->end();
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return getReg(V, BB, It);
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}
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unsigned getReg(Value *V, MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IPt) {
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unsigned &Reg = RegMap[V];
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if (Reg == 0) {
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Reg = makeAnotherReg(V->getType());
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RegMap[V] = Reg;
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}
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// If this operand is a constant, emit the code to copy the constant into
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// the register here...
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//
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if (Constant *C = dyn_cast<Constant>(V)) {
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copyConstantToRegister(MBB, IPt, C, Reg);
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RegMap.erase(V); // Assign a new name to this constant if ref'd again
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} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
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// Move the address of the global into the register
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unsigned TmpReg = makeAnotherReg(V->getType());
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BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
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BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
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.addGlobalAddress (GV);
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RegMap.erase(V); // Assign a new name to this address if ref'd again
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}
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return Reg;
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}
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};
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}
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FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
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return new V8ISel(TM);
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}
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enum TypeClass {
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cByte, cShort, cInt, cLong, cFloat, cDouble
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};
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static TypeClass getClass (const Type *T) {
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switch (T->getPrimitiveID ()) {
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case Type::UByteTyID: case Type::SByteTyID: return cByte;
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case Type::UShortTyID: case Type::ShortTyID: return cShort;
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case Type::UIntTyID: case Type::IntTyID: return cInt;
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case Type::ULongTyID: case Type::LongTyID: return cLong;
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case Type::FloatTyID: return cFloat;
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case Type::DoubleTyID: return cDouble;
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default:
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assert (0 && "Type of unknown class passed to getClass?");
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return cByte;
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}
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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unsigned Class = getClass(C->getType());
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switch (Class) {
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case cByte:
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
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return;
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case cShort: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
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return;
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}
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case cInt: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
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return;
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}
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case cLong: {
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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uint32_t topHalf, bottomHalf;
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topHalf = (uint32_t) (CI->getRawValue () >> 32);
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bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
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return;
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}
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default:
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std::cerr << "Offending constant: " << *C << "\n";
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assert (0 && "Can't copy this kind of constant into register yet");
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return;
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}
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}
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std::cerr << "Offending constant: " << *C << "\n";
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assert (0 && "Can't copy this kind of constant into register yet");
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}
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bool V8ISel::runOnFunction(Function &Fn) {
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// First pass over the function, lower any unknown intrinsic functions
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// with the IntrinsicLowering class.
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LowerUnknownIntrinsicFunctionCalls(Fn);
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F = &MachineFunction::construct(&Fn, TM);
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// Create all of the machine basic blocks for the function...
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for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
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BB = &F->front();
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// Set up a frame object for the return address. This is used by the
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// llvm.returnaddress & llvm.frameaddress intrinisics.
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//ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
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// Copy incoming arguments off of the stack and out of fixed registers.
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//LoadArgumentsToVirtualRegs(Fn);
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// Instruction select everything except PHI nodes
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visit(Fn);
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// Select the PHI nodes
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//SelectPHINodes();
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RegMap.clear();
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MBBMap.clear();
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F = 0;
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// We always build a machine code representation for the function
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return true;
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}
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void V8ISel::visitCallInst(CallInst &I) {
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assert (I.getNumOperands () == 1 && "Can't handle call args yet");
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unsigned DestReg = getReg (I);
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BuildMI (BB, V8::CALL, 1).addPCDisp (I.getOperand (0));
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if (I.getType ()->getPrimitiveID () == Type::VoidTyID)
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return;
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// Deal w/ return value
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switch (getClass (I.getType ())) {
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case cByte:
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case cShort:
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case cInt:
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// Schlep it over into the destination register
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BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
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break;
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default:
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visitInstruction (I);
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return;
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}
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}
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void V8ISel::visitReturnInst(ReturnInst &I) {
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if (I.getNumOperands () == 1) {
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unsigned RetValReg = getReg (I.getOperand (0));
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switch (getClass (I.getOperand (0)->getType ())) {
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case cByte:
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case cShort:
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case cInt:
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// Schlep it over into i0 (where it will become o0 after restore).
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BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
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break;
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default:
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visitInstruction (I);
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return;
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}
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} else if (I.getNumOperands () != 1) {
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visitInstruction (I);
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}
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// Just emit a 'retl' instruction to return.
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BuildMI(BB, V8::RETL, 0);
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return;
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}
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void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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unsigned DestReg = getReg (I);
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unsigned Op0Reg = getReg (I.getOperand (0));
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned ResultReg = makeAnotherReg (I.getType ());
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// FIXME: support long, ulong, fp.
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switch (I.getOpcode ()) {
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case Instruction::Add:
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BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Sub:
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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case Instruction::Mul: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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}
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case Instruction::Div: {
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unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
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// Clear out the Y register (top half of LHS of divide)
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BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
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BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, V8::NOP, 0);
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BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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}
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default:
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visitInstruction (I);
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return;
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}
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switch (getClass (I.getType ())) {
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case cByte:
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if (I.getType ()->isSigned ()) { // add byte
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BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
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} else { // add ubyte
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unsigned TmpReg = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
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BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
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}
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break;
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case cShort:
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if (I.getType ()->isSigned ()) { // add short
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unsigned TmpReg = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
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BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
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} else { // add ushort
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unsigned TmpReg = makeAnotherReg (I.getType ());
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BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
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BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
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}
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break;
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case cInt:
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BuildMI (BB, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (ResultReg);
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break;
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default:
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visitInstruction (I);
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return;
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}
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}
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/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
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/// function, lowering any calls to unknown intrinsic functions into the
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/// equivalent LLVM code.
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void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
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for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
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for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
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if (CallInst *CI = dyn_cast<CallInst>(I++))
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if (Function *F = CI->getCalledFunction())
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switch (F->getIntrinsicID()) {
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case Intrinsic::not_intrinsic: break;
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default:
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// All other intrinsic calls we must lower.
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Instruction *Before = CI->getPrev();
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TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
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if (Before) { // Move iterator to instruction after call
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I = Before; ++I;
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} else {
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I = BB->begin();
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}
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}
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}
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void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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unsigned TmpReg1, TmpReg2;
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switch (ID) {
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default: assert(0 && "Intrinsic not supported!");
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}
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}
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