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https://github.com/c64scene-ar/llvm-6502.git
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00b16889ab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
237 lines
8.3 KiB
C++
237 lines
8.3 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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X86VectorEnum llvm::X86Vector = NoSSE;
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bool llvm::X86ScalarSSE = false;
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/// X86TargetMachineModule - Note that this is used on hosts that cannot link
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/// in a library unless there are references into the library. In particular,
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/// it seems that it is not possible to get things to work on Win32 without
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/// this. Though it is unused, do not remove it.
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extern "C" int X86TargetMachineModule;
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int X86TargetMachineModule = 0;
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namespace {
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cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
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cl::desc("Disable the ssa-based peephole optimizer "
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"(defaults to disabled)"));
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cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
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cl::desc("Disable the X86 asm printer, for use "
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"when profiling the code generator."));
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cl::opt<bool, true> EnableSSEFP("enable-sse-scalar-fp",
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cl::desc("Perform FP math in SSE regs instead of the FP stack"),
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cl::location(X86ScalarSSE),
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cl::init(false));
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// FIXME: This should eventually be handled with target triples and
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// subtarget support!
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cl::opt<X86VectorEnum, true>
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SSEArg(
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cl::desc("Enable SSE support in the X86 target:"),
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cl::values(
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clEnumValN(SSE, "sse", " Enable SSE support"),
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clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
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clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
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clEnumValEnd),
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cl::location(X86Vector), cl::init(NoSSE));
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// Register the target.
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RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
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}
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unsigned X86TargetMachine::getJITMatchQuality() {
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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return 10;
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#else
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return 0;
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#endif
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}
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unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "i[3-9]86-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
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TT[4] == '-' && TT[1] - '3' < 6)
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return 20;
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if (M.getEndianness() == Module::LittleEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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/// X86TargetMachine ctor - Create an ILP32 architecture model
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///
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X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
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: TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
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Subtarget(M),
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FrameInfo(TargetFrameInfo::StackGrowsDown,
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Subtarget.getStackAlignment(), -4),
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JITInfo(*this) {
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// Scalar SSE FP requires at least SSE2
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X86ScalarSSE &= X86Vector >= SSE2;
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}
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// addPassesToEmitFile - We currently use all of the same passes as the JIT
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// does to emit statically compiled machine code.
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bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
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CodeGenFileType FileType) {
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if (FileType != TargetMachine::AssemblyFile &&
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FileType != TargetMachine::ObjectFile) return true;
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// Default to pattern ISel
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if (PatternISelTriState == 0)
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PM.add(createX86SimpleInstructionSelector(*this));
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else
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PM.add(createX86PatternInstructionSelector(*this));
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// Run optional SSA-based machine code optimizations next...
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if (!NoSSAPeephole)
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PM.add(createX86SSAPeepholeOptimizerPass());
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// Print the instruction selected machine code...
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createX86FloatingPointStackifierPass());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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if (PrintMachineCode) // Print the register-allocated code
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PM.add(createX86CodePrinterPass(std::cerr, *this));
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if (!DisableOutput)
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switch (FileType) {
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default:
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assert(0 && "Unexpected filetype here!");
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case TargetMachine::AssemblyFile:
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PM.add(createX86CodePrinterPass(Out, *this));
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break;
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case TargetMachine::ObjectFile:
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// FIXME: We only support emission of ELF files for now, this should check
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// the target triple and decide on the format to write (e.g. COFF on
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// win32).
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addX86ELFObjectWriterPass(PM, Out, *this);
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break;
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}
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false; // success!
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this is
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/// not supported for this target.
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///
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void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// Default to pattern ISel
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if (PatternISelTriState == 0)
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PM.add(createX86SimpleInstructionSelector(TM));
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else
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PM.add(createX86PatternInstructionSelector(TM));
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// Run optional SSA-based machine code optimizations next...
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if (!NoSSAPeephole)
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PM.add(createX86SSAPeepholeOptimizerPass());
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// FIXME: Add SSA based peephole optimizer here.
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// Print the instruction selected machine code...
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createX86FloatingPointStackifierPass());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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if (PrintMachineCode) // Print the register-allocated code
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PM.add(createX86CodePrinterPass(std::cerr, TM));
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}
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bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE) {
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PM.add(createX86CodeEmitterPass(MCE));
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false;
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}
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