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https://github.com/c64scene-ar/llvm-6502.git
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b503b49b51
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
2.4 KiB
LLVM
104 lines
2.4 KiB
LLVM
; Test moves between FPRs and GPRs.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
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; 32 bits of the FPR.
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define float @f1(i32 %a) {
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; CHECK: f1:
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; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
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; CHECK: ldgr %f0, [[REGISTER]]
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Like f1, but create a situation where the shift can be folded with
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; surrounding code.
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define float @f2(i64 %big) {
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; CHECK: f2:
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; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 31
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; CHECK: ldgr %f0, [[REGISTER]]
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%shift = lshr i64 %big, 1
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%a = trunc i64 %shift to i32
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Another example of the same thing.
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define float @f3(i64 %big) {
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; CHECK: f3:
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; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 2
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; CHECK: ldgr %f0, [[REGISTER]]
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%shift = ashr i64 %big, 30
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%a = trunc i64 %shift to i32
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Like f1, but the value to transfer is already in the high 32 bits.
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define float @f4(i64 %big) {
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; CHECK: f4:
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; CHECK-NOT: %r2
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; CHECK: nilf %r2, 0
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; CHECK-NOT: %r2
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; CHECK: ldgr %f0, %r2
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%shift = ashr i64 %big, 32
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%a = trunc i64 %shift to i32
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Test 64-bit moves from GPRs to FPRs.
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define double @f5(i64 %a) {
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; CHECK: f5:
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; CHECK: ldgr %f0, %r2
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%res = bitcast i64 %a to double
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ret double %res
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}
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; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
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; so this goes through memory.
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define void @f6(fp128 *%a, i128 *%b) {
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; CHECK: f6:
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; CHECK: lg
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; CHECK: lg
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; CHECK: stg
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; CHECK: stg
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%val = load i128 *%b
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%res = bitcast i128 %val to fp128
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store fp128 %res, fp128 *%a
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ret void
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}
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; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
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; be moved into the low 32 bits of the GPR.
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define i32 @f7(float %a) {
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; CHECK: f7:
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; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
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; CHECK: srlg %r2, [[REGISTER]], 32
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%res = bitcast float %a to i32
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ret i32 %res
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}
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; Test 64-bit moves from FPRs to GPRs.
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define i64 @f8(double %a) {
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; CHECK: f8:
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; CHECK: lgdr %r2, %f0
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%res = bitcast double %a to i64
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ret i64 %res
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}
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; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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define void @f9(fp128 *%a, i128 *%b) {
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; CHECK: f9:
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; CHECK: ld
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; CHECK: ld
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; CHECK: std
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; CHECK: std
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%val = load fp128 *%a
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%res = bitcast fp128 %val to i128
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store i128 %res, i128 *%b
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ret void
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}
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