Pete Cooper f210b68b41 Target override to allow CodeGenPrepare to sink address operands to intrinsics in the same way it current does for loads and stores ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152666 91177308-0d34-0410-b5e6-96231b3b80d8		2012-03-13 20:59:56 +00:00
..
Mangler.h
Target.td	Specify SubRegIndex components on the index itself.	2012-02-01 23:16:41 +00:00
TargetCallingConv.h
TargetCallingConv.td	Add TableGen support for callee saved registers.	2012-01-17 22:46:58 +00:00
TargetData.h
TargetELFWriterInfo.h
TargetFrameLowering.h
TargetInstrInfo.h	Convert assert(0) to llvm_unreachable	2012-02-05 22:14:15 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h	Convert assert(0) to llvm_unreachable	2012-02-05 22:14:15 +00:00
TargetLibraryInfo.h	Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI calls	2012-02-12 02:15:20 +00:00
TargetLowering.h	Target override to allow CodeGenPrepare to sink address operands to intrinsics in the same way it current does for loads and stores	2012-03-13 20:59:56 +00:00
TargetLoweringObjectFile.h	Modify the code that emits the module flags to use the new module flags accessor	2012-02-15 22:36:15 +00:00
TargetMachine.h	TargetPassConfig: confine the MC configuration to TargetMachine.	2012-02-04 02:56:59 +00:00
TargetOpcodes.h
TargetOptions.h	RegAlloc superpass: includes phi elimination, coalescing, and scheduling.	2012-02-10 04:10:36 +00:00
TargetRegisterInfo.h	MCRegisterInfo-ize getMatchingSuperReg.	2012-03-05 19:33:24 +00:00
TargetSchedule.td
TargetSelectionDAG.td	Improve generated code for extending loads and some trunc stores on ARM.	2012-02-20 09:24:05 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h	Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.	2012-02-22 05:59:10 +00:00