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d151389bd1
CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each dispatch group. The old itinerary entry was just wrong (but has not mattered because we don't generate these instructions). This will matter when, in an upcoming commit, we start generating these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198359 91177308-0d34-0410-b5e6-96231b3b80d8
432 lines
14 KiB
C++
432 lines
14 KiB
C++
//===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements hazard recognizers for scheduling on PowerPC processors.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "PPCHazardRecognizers.h"
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) {
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// FIXME: Move this.
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if (isBCTRAfterSet(SU))
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return true;
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const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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if (!MCID)
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return false;
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if (!MCID->mayLoad())
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return false;
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// SU is a load; for any predecessors in this dispatch group, that are stores,
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// and with which we have an ordering dependency, return true.
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for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
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const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
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if (!PredMCID || !PredMCID->mayStore())
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continue;
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if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
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continue;
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for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
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if (SU->Preds[i].getSUnit() == CurGroup[j])
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return true;
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}
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return false;
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}
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bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) {
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const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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if (!MCID)
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return false;
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if (!MCID->isBranch())
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return false;
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// SU is a branch; for any predecessors in this dispatch group, with which we
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// have a data dependence and set the counter register, return true.
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for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
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const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
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if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
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continue;
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if (SU->Preds[i].isCtrl())
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continue;
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for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
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if (SU->Preds[i].getSUnit() == CurGroup[j])
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return true;
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}
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return false;
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}
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// FIXME: Remove this when we don't need this:
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namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } }
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// FIXME: A lot of code in PPCDispatchGroupSBHazardRecognizer is P7 specific.
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bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
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unsigned &NSlots) {
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// FIXME: Indirectly, this information is contained in the itinerary, and
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// we should derive it from there instead of separately specifying it
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// here.
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unsigned IIC = MCID->getSchedClass();
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switch (IIC) {
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default:
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NSlots = 1;
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break;
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case PPC::Sched::IIC_IntDivW:
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case PPC::Sched::IIC_IntDivD:
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case PPC::Sched::IIC_LdStLoadUpd:
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case PPC::Sched::IIC_LdStLDU:
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case PPC::Sched::IIC_LdStLFDU:
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case PPC::Sched::IIC_LdStLFDUX:
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case PPC::Sched::IIC_LdStLHA:
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case PPC::Sched::IIC_LdStLHAU:
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case PPC::Sched::IIC_LdStLWA:
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case PPC::Sched::IIC_LdStSTDU:
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case PPC::Sched::IIC_LdStSTFDU:
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NSlots = 2;
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break;
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case PPC::Sched::IIC_LdStLoadUpdX:
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case PPC::Sched::IIC_LdStLDUX:
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case PPC::Sched::IIC_LdStLHAUX:
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case PPC::Sched::IIC_LdStLWARX:
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case PPC::Sched::IIC_LdStLDARX:
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case PPC::Sched::IIC_LdStSTDUX:
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case PPC::Sched::IIC_LdStSTDCX:
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case PPC::Sched::IIC_LdStSTWCX:
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case PPC::Sched::IIC_BrMCRX: // mtcr
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// FIXME: Add sync/isync (here and in the itinerary).
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NSlots = 4;
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break;
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}
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// FIXME: record-form instructions need a different itinerary class.
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if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
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NSlots = 2;
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switch (IIC) {
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default:
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// All multi-slot instructions must come first.
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return NSlots > 1;
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case PPC::Sched::IIC_BrCR: // cr logicals
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case PPC::Sched::IIC_SprMFCR:
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case PPC::Sched::IIC_SprMFCRF:
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case PPC::Sched::IIC_SprMTSPR:
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return true;
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}
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}
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ScheduleHazardRecognizer::HazardType
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PPCDispatchGroupSBHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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if (Stalls == 0 && isLoadAfterStore(SU))
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return NoopHazard;
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return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
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}
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bool PPCDispatchGroupSBHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
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const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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unsigned NSlots;
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if (MCID && mustComeFirst(MCID, NSlots) && CurSlots)
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return true;
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return ScoreboardHazardRecognizer::ShouldPreferAnother(SU);
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}
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unsigned PPCDispatchGroupSBHazardRecognizer::PreEmitNoops(SUnit *SU) {
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// We only need to fill out a maximum of 5 slots here: The 6th slot could
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// only be a second branch, and otherwise the next instruction will start a
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// new group.
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if (isLoadAfterStore(SU) && CurSlots < 6) {
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unsigned Directive =
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DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
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// If we're using a special group-terminating nop, then we need only one.
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if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7)
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return 1;
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return 5 - CurSlots;
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}
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return ScoreboardHazardRecognizer::PreEmitNoops(SU);
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}
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void PPCDispatchGroupSBHazardRecognizer::EmitInstruction(SUnit *SU) {
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const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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if (MCID) {
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if (CurSlots == 5 || (MCID->isBranch() && CurBranches == 1)) {
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CurGroup.clear();
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CurSlots = CurBranches = 0;
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} else {
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DEBUG(dbgs() << "**** Adding to dispatch group: SU(" <<
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SU->NodeNum << "): ");
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DEBUG(DAG->dumpNode(SU));
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unsigned NSlots;
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bool MustBeFirst = mustComeFirst(MCID, NSlots);
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// If this instruction must come first, but does not, then it starts a
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// new group.
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if (MustBeFirst && CurSlots) {
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CurSlots = CurBranches = 0;
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CurGroup.clear();
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}
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CurSlots += NSlots;
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CurGroup.push_back(SU);
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if (MCID->isBranch())
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++CurBranches;
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}
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}
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return ScoreboardHazardRecognizer::EmitInstruction(SU);
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}
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void PPCDispatchGroupSBHazardRecognizer::AdvanceCycle() {
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return ScoreboardHazardRecognizer::AdvanceCycle();
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}
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void PPCDispatchGroupSBHazardRecognizer::RecedeCycle() {
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llvm_unreachable("Bottom-up scheduling not supported");
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}
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void PPCDispatchGroupSBHazardRecognizer::Reset() {
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CurGroup.clear();
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CurSlots = CurBranches = 0;
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return ScoreboardHazardRecognizer::Reset();
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}
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void PPCDispatchGroupSBHazardRecognizer::EmitNoop() {
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unsigned Directive =
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DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
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// If the group has now filled all of its slots, or if we're using a special
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// group-terminating nop, the group is complete.
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if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 ||
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CurSlots == 6) {
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CurGroup.clear();
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CurSlots = CurBranches = 0;
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} else {
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CurGroup.push_back(0);
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++CurSlots;
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}
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}
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//===----------------------------------------------------------------------===//
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// PowerPC 970 Hazard Recognizer
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//
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// This models the dispatch group formation of the PPC970 processor. Dispatch
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// groups are bundles of up to five instructions that can contain various mixes
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// of instructions. The PPC970 can dispatch a peak of 4 non-branch and one
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// branch instruction per-cycle.
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//
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// There are a number of restrictions to dispatch group formation: some
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// instructions can only be issued in the first slot of a dispatch group, & some
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// instructions fill an entire dispatch group. Additionally, only branches can
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// issue in the 5th (last) slot.
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//
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// Finally, there are a number of "structural" hazards on the PPC970. These
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// conditions cause large performance penalties due to misprediction, recovery,
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// and replay logic that has to happen. These cases include setting a CTR and
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// branching through it in the same dispatch group, and storing to an address,
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// then loading from the same address within a dispatch group. To avoid these
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// conditions, we insert no-op instructions when appropriate.
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//
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// FIXME: This is missing some significant cases:
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// 1. Modeling of microcoded instructions.
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// 2. Handling of serialized operations.
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// 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
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//
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PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetMachine &TM)
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: TM(TM) {
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::EndDispatchGroup() {
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DEBUG(errs() << "=== Start of dispatch group\n");
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NumIssued = 0;
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// Structural hazard info.
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HasCTRSet = false;
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NumStores = 0;
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}
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PPCII::PPC970_Unit
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PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
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bool &isFirst, bool &isSingle,
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bool &isCracked,
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bool &isLoad, bool &isStore) {
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const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode);
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isLoad = MCID.mayLoad();
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isStore = MCID.mayStore();
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uint64_t TSFlags = MCID.TSFlags;
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isFirst = TSFlags & PPCII::PPC970_First;
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isSingle = TSFlags & PPCII::PPC970_Single;
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isCracked = TSFlags & PPCII::PPC970_Cracked;
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return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
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}
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/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
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/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
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bool PPCHazardRecognizer970::
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isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
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const Value *LoadValue) const {
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for (unsigned i = 0, e = NumStores; i != e; ++i) {
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// Handle exact and commuted addresses.
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if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i])
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return true;
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// Okay, we don't have an exact match, if this is an indexed offset, see if
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// we have overlap (which happens during fp->int conversion for example).
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if (StoreValue[i] == LoadValue) {
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// Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
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// to see if the load and store actually overlap.
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if (StoreOffset[i] < LoadOffset) {
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if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset) return true;
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} else {
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if (int64_t(LoadOffset+LoadSize) > StoreOffset[i]) return true;
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}
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}
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}
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return false;
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}
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/// getHazardType - We return hazard for any non-branch instruction that would
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/// terminate the dispatch group. We turn NoopHazard for any
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/// instructions that wouldn't terminate the dispatch group that would cause a
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/// pipeline flush.
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ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
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getHazardType(SUnit *SU, int Stalls) {
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assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead");
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MachineInstr *MI = SU->getInstr();
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if (MI->isDebugValue())
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return NoHazard;
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unsigned Opcode = MI->getOpcode();
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bool isFirst, isSingle, isCracked, isLoad, isStore;
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PPCII::PPC970_Unit InstrType =
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GetInstrType(Opcode, isFirst, isSingle, isCracked,
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isLoad, isStore);
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if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
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// We can only issue a PPC970_First/PPC970_Single instruction (such as
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// crand/mtspr/etc) if this is the first cycle of the dispatch group.
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if (NumIssued != 0 && (isFirst || isSingle))
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return Hazard;
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// If this instruction is cracked into two ops by the decoder, we know that
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// it is not a branch and that it cannot issue if 3 other instructions are
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// already in the dispatch group.
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if (isCracked && NumIssued > 2)
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return Hazard;
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switch (InstrType) {
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default: llvm_unreachable("Unknown instruction type!");
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case PPCII::PPC970_FXU:
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case PPCII::PPC970_LSU:
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case PPCII::PPC970_FPU:
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case PPCII::PPC970_VALU:
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case PPCII::PPC970_VPERM:
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// We can only issue a branch as the last instruction in a group.
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if (NumIssued == 4) return Hazard;
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break;
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case PPCII::PPC970_CRU:
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// We can only issue a CR instruction in the first two slots.
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if (NumIssued >= 2) return Hazard;
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break;
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case PPCII::PPC970_BRU:
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break;
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}
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// Do not allow MTCTR and BCTRL to be in the same dispatch group.
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if (HasCTRSet && Opcode == PPC::BCTRL)
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return NoopHazard;
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// If this is a load following a store, make sure it's not to the same or
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// overlapping address.
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if (isLoad && NumStores && !MI->memoperands_empty()) {
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MachineMemOperand *MO = *MI->memoperands_begin();
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if (isLoadOfStoredAddress(MO->getSize(),
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MO->getOffset(), MO->getValue()))
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return NoopHazard;
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}
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return NoHazard;
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}
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void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
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MachineInstr *MI = SU->getInstr();
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if (MI->isDebugValue())
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return;
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unsigned Opcode = MI->getOpcode();
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bool isFirst, isSingle, isCracked, isLoad, isStore;
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PPCII::PPC970_Unit InstrType =
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GetInstrType(Opcode, isFirst, isSingle, isCracked,
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isLoad, isStore);
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if (InstrType == PPCII::PPC970_Pseudo) return;
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// Update structural hazard information.
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if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
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// Track the address stored to.
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if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
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MachineMemOperand *MO = *MI->memoperands_begin();
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StoreSize[NumStores] = MO->getSize();
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StoreOffset[NumStores] = MO->getOffset();
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StoreValue[NumStores] = MO->getValue();
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++NumStores;
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}
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if (InstrType == PPCII::PPC970_BRU || isSingle)
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NumIssued = 4; // Terminate a d-group.
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++NumIssued;
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// If this instruction is cracked into two ops by the decoder, remember that
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// we issued two pieces.
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if (isCracked)
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++NumIssued;
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if (NumIssued == 5)
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::AdvanceCycle() {
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assert(NumIssued < 5 && "Illegal dispatch group!");
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++NumIssued;
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if (NumIssued == 5)
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::Reset() {
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EndDispatchGroup();
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}
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