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Fixed print immediate Fixed Identation on MipsISelDAGToDAG.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39764 91177308-0d34-0410-b5e6-96231b3b80d8
273 lines
7.9 KiB
C++
273 lines
7.9 KiB
C++
//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "Mips.h"
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#include "MipsISelLowering.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
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/// TM - Keep a reference to MipsTargetMachine.
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MipsTargetMachine &TM;
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/// MipsLowering - This object fully describes how to lower LLVM code to an
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/// Mips-specific SelectionDAG.
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MipsTargetLowering MipsLowering;
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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//TODO: add initialization on constructor
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//const MipsSubtarget *Subtarget;
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public:
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MipsDAGToDAGISel(MipsTargetMachine &tm) :
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SelectionDAGISel(MipsLowering),
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TM(tm), MipsLowering(*TM.getTargetLowering()) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD);
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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SDNode *Select(SDOperand N);
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// Complex Pattern.
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bool SelectAddr(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset);
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// getI32Imm - Return a target constant with the specified
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// value, of type i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void MipsDAGToDAGISel::
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InstructionSelectBasicBlock(SelectionDAG &SD)
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{
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DEBUG(BB->dump());
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// Codegen the basic block.
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#ifndef NDEBUG
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DOUT << "===== Instruction selection begins:\n";
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Indent = 0;
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#endif
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// Select target instructions for the DAG.
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SD.setRoot(SelectRoot(SD.getRoot()));
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#ifndef NDEBUG
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DOUT << "===== Instruction selection ends:\n";
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#endif
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SD.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(SD);
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::
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SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
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{
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// TargetExternalSymbol and TargetGlobalAddress are
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// lowered and their addresses go into registers, so
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// they should not be touched here.
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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// Operand is an result from an ADD.
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if (Addr.getOpcode() == ISD::ADD)
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{
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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{
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if (Predicate_immSExt16(CN))
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{
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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SDNode* MipsDAGToDAGISel::
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Select(SDOperand N)
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{
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SDNode *Node = N.Val;
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unsigned Opcode = Node->getOpcode();
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// Dump information about the Node being selected
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#ifndef NDEBUG
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DOUT << std::string(Indent, ' ') << "Selecting: ";
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DEBUG(Node->dump(CurDAG));
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DOUT << "\n";
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Indent += 2;
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#endif
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// If we have a custom node, we already have selected!
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if (Opcode >= ISD::BUILTIN_OP_END && Opcode < MipsISD::FIRST_NUMBER) {
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "== ";
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DEBUG(Node->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return NULL;
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}
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///
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// Instruction Selection not handled by custom or by the
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// auto-generated tablegen selection should be handled here
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///
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switch(Opcode) {
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default: break;
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/// Special Mul operations
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case ISD::MULHS:
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case ISD::MULHU: {
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SDOperand MulOp1 = Node->getOperand(0);
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SDOperand MulOp2 = Node->getOperand(1);
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AddToISelQueue(MulOp1);
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AddToISelQueue(MulOp2);
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unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
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SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
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SDOperand MFInFlag = SDOperand(MulNode, 0);
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return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
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}
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/// Div operations
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case ISD::SDIV:
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case ISD::UDIV: {
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SDOperand DivOp1 = Node->getOperand(0);
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SDOperand DivOp2 = Node->getOperand(1);
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AddToISelQueue(DivOp1);
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AddToISelQueue(DivOp2);
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unsigned DivOp = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
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SDNode *DivNode = CurDAG->getTargetNode(DivOp, MVT::Flag, DivOp1, DivOp2);
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SDOperand MFInFlag = SDOperand(DivNode, 0);
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return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MFInFlag);
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}
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/// Rem operations
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case ISD::SREM:
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case ISD::UREM: {
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SDOperand RemOp1 = Node->getOperand(0);
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SDOperand RemOp2 = Node->getOperand(1);
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AddToISelQueue(RemOp1);
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AddToISelQueue(RemOp2);
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unsigned RemOp = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
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SDNode *RemNode = CurDAG->getTargetNode(RemOp, MVT::Flag, RemOp1, RemOp2);
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SDOperand MFInFlag = SDOperand(RemNode, 0);
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return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
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}
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}
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// Select the default instruction
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SDNode *ResNode = SelectCode(N);
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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if (ResNode == NULL || ResNode == N.Val)
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DEBUG(N.Val->dump(CurDAG));
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else
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DEBUG(ResNode->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return ResNode;
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}
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/// createMipsISelDag - This pass converts a legalized DAG into a
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/// MIPS-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
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return new MipsDAGToDAGISel(TM);
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}
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