mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2df483efb3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
483 lines
20 KiB
TableGen
483 lines
20 KiB
TableGen
//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips DSP ASE instructions.
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//
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//===----------------------------------------------------------------------===//
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// ImmLeaf
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def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
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def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
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def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
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def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
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def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
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def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
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// Mips-specific dsp nodes
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def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
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def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
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class MipsDSPBase<string Opc, SDTypeProfile Prof> :
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SDNode<!strconcat("MipsISD::", Opc), Prof,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
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class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
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SDNode<!strconcat("MipsISD::", Opc), Prof,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
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def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
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def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
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def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
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def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
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def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
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def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
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def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
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def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>;
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def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
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def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
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def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
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def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
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def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
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def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
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def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
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def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
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def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
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def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
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def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
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def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
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def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
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def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
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def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
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def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
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def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
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def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
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def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
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def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
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def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
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def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
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def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
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def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
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def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
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def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
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def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
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def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
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// Flags.
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class IsCommutable {
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bit isCommutable = 1;
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}
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class UseAC {
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list<Register> Uses = [AC0];
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}
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// Instruction encoding.
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class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
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class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
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class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
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class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
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class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
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class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
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class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
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class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
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class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
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class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
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class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
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class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
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class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
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class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
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class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
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class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
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class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
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class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
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class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
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class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
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class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
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class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
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class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
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class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
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class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
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class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
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class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
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class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
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class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
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class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
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class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
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class SHILO_ENC : SHILO_R1_FMT<0b11010>;
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class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
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class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
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class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
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class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
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class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
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class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
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class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
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class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
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class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
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class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
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class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
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// Instruction desc.
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
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Instruction realinst> :
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PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>,
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PseudoInstExpansion<(realinst AC0, simm16:$shift)> {
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list<Register> Defs = [DSPCtrl, AC0];
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list<Register> Uses = [AC0];
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InstrItinClass Itinerary = itin;
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}
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class SHILO_R1_DESC_BASE<string instr_asm> {
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dag OutOperandList = (outs ACRegs:$ac);
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dag InOperandList = (ins simm16:$shift);
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string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
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}
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class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
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Instruction realinst> :
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PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>,
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PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> {
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list<Register> Defs = [DSPCtrl, AC0];
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list<Register> Uses = [AC0];
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InstrItinClass Itinerary = itin;
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}
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class SHILO_R2_DESC_BASE<string instr_asm> {
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dag OutOperandList = (outs ACRegs:$ac);
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dag InOperandList = (ins CPURegs:$rs);
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string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
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}
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class MTHLIP_DESC_BASE<string instr_asm> {
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dag OutOperandList = (outs ACRegs:$ac);
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dag InOperandList = (ins CPURegs:$rs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
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}
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class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
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Instruction realinst> :
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PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
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[(OpNode CPURegs:$rs, CPURegs:$rt)]>,
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PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
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list<Register> Defs = [DSPCtrl, AC0];
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list<Register> Uses = [AC0];
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InstrItinClass Itinerary = itin;
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}
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class DPA_W_PH_DESC_BASE<string instr_asm> {
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dag OutOperandList = (outs ACRegs:$ac);
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dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
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string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
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}
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class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
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Instruction realinst> :
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PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
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[(OpNode CPURegs:$rs, CPURegs:$rt)]>,
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PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
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list<Register> Defs = [DSPCtrl, AC0];
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InstrItinClass Itinerary = itin;
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}
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class MULT_DESC_BASE<string instr_asm> {
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dag OutOperandList = (outs ACRegs:$ac);
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dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
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string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
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}
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 1
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//===----------------------------------------------------------------------===//
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// Multiplication
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class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">;
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class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">;
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class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">;
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class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">;
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class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">;
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// Dot product with accumulate/subtract
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class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">;
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class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">;
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class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">;
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class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">;
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class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">;
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class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">;
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class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">;
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class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">;
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class MULT_DSP_DESC : MULT_DESC_BASE<"mult">;
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class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">;
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class MADD_DSP_DESC : MULT_DESC_BASE<"madd">;
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class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">;
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class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">;
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class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">;
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// Extr
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class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
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class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
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class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
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class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
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NoItinerary>;
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class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
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class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
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NoItinerary>;
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class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
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NoItinerary>;
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class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
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NoItinerary>;
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class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
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NoItinerary>;
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class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
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NoItinerary>;
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class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
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NoItinerary>;
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class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
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NoItinerary>;
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class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">;
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class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">;
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class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 2
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// Dot product with accumulate/subtract
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class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">;
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class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">;
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class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">;
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class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">;
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class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">;
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class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">;
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class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">;
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class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">;
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class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">;
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// Instruction defs.
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// MIPS DSP Rev 1
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def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
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def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
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def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
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def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
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def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
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def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
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def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
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def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
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def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
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def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
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def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
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def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
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def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
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def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
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def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
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def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
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def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
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def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
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def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
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def EXTP : EXTP_ENC, EXTP_DESC;
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def EXTPV : EXTPV_ENC, EXTPV_DESC;
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def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
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def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
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def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
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def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
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def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
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def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
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def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
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def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
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def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
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def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
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def SHILO : SHILO_ENC, SHILO_DESC;
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def SHILOV : SHILOV_ENC, SHILOV_DESC;
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def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
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// MIPS DSP Rev 2
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let Predicates = [HasDSPR2] in {
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def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
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def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
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def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
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def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
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def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
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def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
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def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
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def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
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def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
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}
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// Pseudos.
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def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary,
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MULSAQ_S_W_PH>;
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def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary,
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MAQ_S_W_PHL>;
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def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary,
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MAQ_S_W_PHR>;
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def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary,
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MAQ_SA_W_PHL>;
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def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary,
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MAQ_SA_W_PHR>;
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def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary,
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DPAU_H_QBL>;
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def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary,
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DPAU_H_QBR>;
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def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary,
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DPSU_H_QBL>;
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def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary,
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DPSU_H_QBR>;
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def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary,
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DPAQ_S_W_PH>;
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def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary,
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DPSQ_S_W_PH>;
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def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary,
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DPAQ_SA_L_W>;
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def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary,
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DPSQ_SA_L_W>;
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def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>,
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IsCommutable;
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def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>,
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IsCommutable;
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def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>,
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IsCommutable, UseAC;
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def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>,
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IsCommutable, UseAC;
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def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>,
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UseAC;
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def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>,
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UseAC;
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def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>;
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def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>;
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def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>;
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let Predicates = [HasDSPR2] in {
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def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>;
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def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>;
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def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary,
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DPAQX_S_W_PH>;
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def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary,
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DPAQX_SA_W_PH>;
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def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary,
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DPAX_W_PH>;
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def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary,
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DPSX_W_PH>;
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def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary,
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DPSQX_S_W_PH>;
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def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary,
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DPSQX_SA_W_PH>;
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def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary,
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MULSA_W_PH>;
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}
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// Patterns.
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class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
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Pat<pattern, result>, Requires<[pred]>;
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class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
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RegisterClass SrcRC> :
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DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
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(COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
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def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
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def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
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def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
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def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
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def : DSPPat<(v2i16 (load addr:$a)),
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(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(v4i8 (load addr:$a)),
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(v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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// Extr patterns.
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
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class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
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