llvm-6502/test/CodeGen
Richard Sandiford 2e015ef9bb [SystemZ] Use MVC for simple load/store pairs
Look for patterns of the form (store (load ...), ...) in which the two
locations are known not to partially overlap.  (Identical locations are OK.)
These sequences are better implemented by MVC unless either the load or
the store could use RELATIVE LONG instructions.

The testcase showed that we weren't using LHRL and LGHRL for extload16,
only sextloadi16.  The patch fixes that too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185919 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 09:46:39 +00:00
..
AArch64 AArch64: correct CodeGen of MOVZ/MOVK combinations. 2013-07-01 19:23:10 +00:00
ARM Add a comment to this change, requested by Eric Christopher. 2013-07-08 19:52:51 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips [mips] Fix test case to check that mips64 instructions are generated. 2013-07-01 20:18:58 +00:00
MSP430 Really fix the test. Sorry for the breakage... 2013-07-01 19:51:36 +00:00
NVPTX [NVPTX] Add support for module-scope inline asm 2013-07-01 13:00:14 +00:00
PowerPC PPC: Allocate RS spill slot for unaligned i64 load/store 2013-07-09 06:34:51 +00:00
R600 Prefix failing commands with not to make clear they are expected to fail. 2013-07-03 16:41:29 +00:00
SI Add R600 backend 2012-12-11 21:25:42 +00:00
SPARC
SystemZ [SystemZ] Use MVC for simple load/store pairs 2013-07-09 09:46:39 +00:00
Thumb
Thumb2
X86 Stop emitting weak symbols into the "coal" sections. 2013-07-08 21:34:52 +00:00
XCore [XCore] Add ISel pattern for LDWCP 2013-07-03 07:48:50 +00:00