mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a85644459c
For ARM on linux we use /proc/cpuinfo to detect the host CPU's features. Linux derives these values without ever looking at the vendor of the specific CPU implementation. Hence, it adds little value, if we parse the output of /proc/cpuinfo only for certain vendors. This patch enables us to derive the correct feature flags e.g. for Qualcomm CPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183790 91177308-0d34-0410-b5e6-96231b3b80d8
615 lines
21 KiB
C++
615 lines
21 KiB
C++
//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This header file implements the operating system Host concept.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/Host.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Config/config.h"
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#include "llvm/Support/DataStream.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <string.h>
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// Include the platform-specific parts of this class.
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#ifdef LLVM_ON_UNIX
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#include "Unix/Host.inc"
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#endif
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#ifdef LLVM_ON_WIN32
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#include "Windows/Host.inc"
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#endif
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#ifdef _MSC_VER
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#include <intrin.h>
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#endif
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#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
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#include <mach/mach.h>
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#include <mach/mach_host.h>
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#include <mach/host_info.h>
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#include <mach/machine.h>
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#endif
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//===----------------------------------------------------------------------===//
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//
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// Implementations of the CPU detection routines
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//
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//===----------------------------------------------------------------------===//
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using namespace llvm;
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuid(registers, value);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#else
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return true;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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// pedantic #else returns to appease -Wunreachable-code (so we don't generate
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// postprocessed code that looks like "return true; return false;")
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#else
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return true;
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#endif
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#else
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return true;
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#endif
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}
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static bool OSHasAVXSupport() {
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#if defined(__GNUC__)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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int rEAX, rEDX;
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__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
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#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
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unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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#else
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int rEAX = 0; // Ensures we return false
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#endif
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return (rEAX & 6) == 6;
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}
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static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
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unsigned &Model) {
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Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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if (Family == 6 || Family == 0xf) {
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if (Family == 0xf)
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// Examine extended family ID if family ID is F.
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Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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// Examine extended model ID if family ID is 6 or F.
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Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
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}
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}
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std::string sys::getHostCPUName() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = 0;
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unsigned Model = 0;
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DetectX86FamilyModel(EAX, Family, Model);
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bool HasSSE3 = (ECX & 0x1);
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// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
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// indicates that the AVX registers will be saved and restored on context
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// switch, then we have full AVX support.
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const unsigned AVXBits = (1 << 27) | (1 << 28);
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bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
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GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = (EDX >> 29) & 0x1;
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union {
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unsigned u[3];
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char c[12];
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} text;
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GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
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if (memcmp(text.c, "GenuineIntel", 12) == 0) {
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switch (Family) {
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case 3:
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return "i386";
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case 4:
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switch (Model) {
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case 0: // Intel486 DX processors
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case 1: // Intel486 DX processors
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case 2: // Intel486 SX processors
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case 3: // Intel487 processors, IntelDX2 OverDrive processors,
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// IntelDX2 processors
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case 4: // Intel486 SL processor
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case 5: // IntelSX2 processors
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case 7: // Write-Back Enhanced IntelDX2 processors
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case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
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default: return "i486";
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}
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case 5:
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switch (Model) {
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case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
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// Pentium processors (60, 66)
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case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
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// 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
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// 150, 166, 200)
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case 3: // Pentium OverDrive processors for Intel486 processor-based
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// systems
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return "pentium";
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case 4: // Pentium OverDrive processor with MMX technology for Pentium
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// processor (75, 90, 100, 120, 133), Pentium processor with
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// MMX technology (166, 200)
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return "pentium-mmx";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 1: // Pentium Pro processor
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return "pentiumpro";
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case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
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// model 03
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case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
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// model 05, and Intel Celeron processor, model 05
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case 6: // Celeron processor, model 06
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return "pentium2";
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case 7: // Pentium III processor, model 07, and Pentium III Xeon
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// processor, model 07
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case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
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// model 08, and Celeron processor, model 08
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case 10: // Pentium III Xeon processor, model 0Ah
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case 11: // Pentium III processor, model 0Bh
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return "pentium3";
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case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
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case 13: // Intel Pentium M processor, Intel Celeron M processor, model
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// 0Dh. All processors are manufactured using the 90 nm process.
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return "pentium-m";
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case 14: // Intel Core Duo processor, Intel Core Solo processor, model
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// 0Eh. All processors are manufactured using the 65 nm process.
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return "yonah";
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case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
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// processor, Intel Core 2 Quad processor, Intel Core 2 Quad
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// mobile processor, Intel Core 2 Extreme processor, Intel
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// Pentium Dual-Core processor, Intel Xeon processor, model
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// 0Fh. All processors are manufactured using the 65 nm process.
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case 22: // Intel Celeron processor model 16h. All processors are
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// manufactured using the 65 nm process
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return "core2";
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case 21: // Intel EP80579 Integrated Processor and Intel EP80579
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// Integrated Processor with Intel QuickAssist Technology
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return "i686"; // FIXME: ???
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case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
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// 17h. All processors are manufactured using the 45 nm process.
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//
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// 45nm: Penryn , Wolfdale, Yorkfield (XE)
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return "penryn";
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case 26: // Intel Core i7 processor and Intel Xeon processor. All
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// processors are manufactured using the 45 nm process.
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case 29: // Intel Xeon processor MP. All processors are manufactured using
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// the 45 nm process.
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case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
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// As found in a Summer 2010 model iMac.
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case 37: // Intel Core i7, laptop version.
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case 44: // Intel Core i7 processor and Intel Xeon processor. All
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// processors are manufactured using the 32 nm process.
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case 46: // Nehalem EX
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case 47: // Westmere EX
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return "corei7";
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// SandyBridge:
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case 42: // Intel Core i7 processor. All processors are manufactured
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// using the 32 nm process.
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case 45:
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// Not all Sandy Bridge processors support AVX (such as the Pentium
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// versions instead of the i7 versions).
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return HasAVX ? "corei7-avx" : "corei7";
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// Ivy Bridge:
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case 58:
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// Not all Ivy Bridge processors support AVX (such as the Pentium
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// versions instead of the i7 versions).
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return HasAVX ? "core-avx-i" : "corei7";
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case 28: // Most 45 nm Intel Atom processors
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case 38: // 45 nm Atom Lincroft
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case 39: // 32 nm Atom Medfield
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case 53: // 32 nm Atom Midview
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case 54: // 32 nm Atom Midview
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return "atom";
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default: return (Em64T) ? "x86-64" : "i686";
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}
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case 15: {
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switch (Model) {
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case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
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// model 00h and manufactured using the 0.18 micron process.
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case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
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// processor MP, and Intel Celeron processor. All processors are
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// model 01h and manufactured using the 0.18 micron process.
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case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
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// Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
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// processor, and Mobile Intel Celeron processor. All processors
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// are model 02h and manufactured using the 0.13 micron process.
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return (Em64T) ? "x86-64" : "pentium4";
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case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
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// processor. All processors are model 03h and manufactured using
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// the 90 nm process.
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case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
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// Pentium D processor, Intel Xeon processor, Intel Xeon
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// processor MP, Intel Celeron D processor. All processors are
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// model 04h and manufactured using the 90 nm process.
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case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
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// Extreme Edition, Intel Xeon processor, Intel Xeon processor
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// MP, Intel Celeron D processor. All processors are model 06h
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// and manufactured using the 65 nm process.
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return (Em64T) ? "nocona" : "prescott";
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default:
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return (Em64T) ? "x86-64" : "pentium4";
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}
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}
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default:
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return "generic";
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}
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} else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
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// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
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// appears to be no way to generate the wide variety of AMD-specific targets
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// from the information returned from CPUID.
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switch (Family) {
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 6:
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case 7: return "k6";
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case 8: return "k6-2";
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case 9:
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case 13: return "k6-3";
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case 10: return "geode";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 4: return "athlon-tbird";
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case 6:
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case 7:
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case 8: return "athlon-mp";
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case 10: return "athlon-xp";
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default: return "athlon";
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}
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case 15:
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if (HasSSE3)
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return "k8-sse3";
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switch (Model) {
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case 1: return "opteron";
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case 5: return "athlon-fx"; // also opteron
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default: return "athlon64";
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}
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case 16:
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return "amdfam10";
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case 20:
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return "btver1";
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case 21:
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if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
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return "btver1";
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if (Model > 15 && Model <= 31)
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return "bdver2";
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return "bdver1";
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case 22:
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if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
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return "btver1";
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return "btver2";
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default:
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return "generic";
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}
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}
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return "generic";
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}
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#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
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std::string sys::getHostCPUName() {
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host_basic_info_data_t hostInfo;
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mach_msg_type_number_t infoCount;
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infoCount = HOST_BASIC_INFO_COUNT;
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host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
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&infoCount);
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if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
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switch(hostInfo.cpu_subtype) {
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case CPU_SUBTYPE_POWERPC_601: return "601";
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case CPU_SUBTYPE_POWERPC_602: return "602";
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case CPU_SUBTYPE_POWERPC_603: return "603";
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case CPU_SUBTYPE_POWERPC_603e: return "603e";
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case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
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case CPU_SUBTYPE_POWERPC_604: return "604";
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case CPU_SUBTYPE_POWERPC_604e: return "604e";
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case CPU_SUBTYPE_POWERPC_620: return "620";
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case CPU_SUBTYPE_POWERPC_750: return "750";
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case CPU_SUBTYPE_POWERPC_7400: return "7400";
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case CPU_SUBTYPE_POWERPC_7450: return "7450";
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case CPU_SUBTYPE_POWERPC_970: return "970";
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default: ;
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}
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return "generic";
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}
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#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
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std::string sys::getHostCPUName() {
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// Access to the Processor Version Register (PVR) on PowerPC is privileged,
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// and so we must use an operating-system interface to determine the current
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// processor type. On Linux, this is exposed through the /proc/cpuinfo file.
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const char *generic = "generic";
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// Note: We cannot mmap /proc/cpuinfo here and then process the resulting
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// memory buffer because the 'file' has 0 size (it can be read from only
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// as a stream).
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std::string Err;
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DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
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if (!DS) {
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DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
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return generic;
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}
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// The cpu line is second (after the 'processor: 0' line), so if this
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// buffer is too small then something has changed (or is wrong).
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char buffer[1024];
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size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
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delete DS;
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const char *CPUInfoStart = buffer;
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const char *CPUInfoEnd = buffer + CPUInfoSize;
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const char *CIP = CPUInfoStart;
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const char *CPUStart = 0;
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size_t CPULen = 0;
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// We need to find the first line which starts with cpu, spaces, and a colon.
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// After the colon, there may be some additional spaces and then the cpu type.
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while (CIP < CPUInfoEnd && CPUStart == 0) {
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if (CIP < CPUInfoEnd && *CIP == '\n')
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == 'c') {
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == 'p') {
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == 'u') {
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++CIP;
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while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
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++CIP;
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if (CIP < CPUInfoEnd && *CIP == ':') {
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++CIP;
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while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
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++CIP;
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if (CIP < CPUInfoEnd) {
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CPUStart = CIP;
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while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
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*CIP != ',' && *CIP != '\n'))
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++CIP;
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CPULen = CIP - CPUStart;
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}
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}
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}
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}
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}
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if (CPUStart == 0)
|
|
while (CIP < CPUInfoEnd && *CIP != '\n')
|
|
++CIP;
|
|
}
|
|
|
|
if (CPUStart == 0)
|
|
return generic;
|
|
|
|
return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
|
|
.Case("604e", "604e")
|
|
.Case("604", "604")
|
|
.Case("7400", "7400")
|
|
.Case("7410", "7400")
|
|
.Case("7447", "7400")
|
|
.Case("7455", "7450")
|
|
.Case("G4", "g4")
|
|
.Case("POWER4", "970")
|
|
.Case("PPC970FX", "970")
|
|
.Case("PPC970MP", "970")
|
|
.Case("G5", "g5")
|
|
.Case("POWER5", "g5")
|
|
.Case("A2", "a2")
|
|
.Case("POWER6", "pwr6")
|
|
.Case("POWER7", "pwr7")
|
|
.Default(generic);
|
|
}
|
|
#elif defined(__linux__) && defined(__arm__)
|
|
std::string sys::getHostCPUName() {
|
|
// The cpuid register on arm is not accessible from user space. On Linux,
|
|
// it is exposed through the /proc/cpuinfo file.
|
|
// Note: We cannot mmap /proc/cpuinfo here and then process the resulting
|
|
// memory buffer because the 'file' has 0 size (it can be read from only
|
|
// as a stream).
|
|
|
|
std::string Err;
|
|
DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
|
|
if (!DS) {
|
|
DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
|
|
return "generic";
|
|
}
|
|
|
|
// Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
|
|
// in all cases.
|
|
char buffer[1024];
|
|
size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
|
|
delete DS;
|
|
|
|
StringRef Str(buffer, CPUInfoSize);
|
|
|
|
SmallVector<StringRef, 32> Lines;
|
|
Str.split(Lines, "\n");
|
|
|
|
// Look for the CPU implementer line.
|
|
StringRef Implementer;
|
|
for (unsigned I = 0, E = Lines.size(); I != E; ++I)
|
|
if (Lines[I].startswith("CPU implementer"))
|
|
Implementer = Lines[I].substr(15).ltrim("\t :");
|
|
|
|
if (Implementer == "0x41") // ARM Ltd.
|
|
// Look for the CPU part line.
|
|
for (unsigned I = 0, E = Lines.size(); I != E; ++I)
|
|
if (Lines[I].startswith("CPU part"))
|
|
// The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
|
|
// values correspond to the "Part number" in the CP15/c0 register. The
|
|
// contents are specified in the various processor manuals.
|
|
return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
|
|
.Case("0x926", "arm926ej-s")
|
|
.Case("0xb02", "mpcore")
|
|
.Case("0xb36", "arm1136j-s")
|
|
.Case("0xb56", "arm1156t2-s")
|
|
.Case("0xb76", "arm1176jz-s")
|
|
.Case("0xc08", "cortex-a8")
|
|
.Case("0xc09", "cortex-a9")
|
|
.Case("0xc0f", "cortex-a15")
|
|
.Case("0xc20", "cortex-m0")
|
|
.Case("0xc23", "cortex-m3")
|
|
.Case("0xc24", "cortex-m4")
|
|
.Default("generic");
|
|
|
|
return "generic";
|
|
}
|
|
#else
|
|
std::string sys::getHostCPUName() {
|
|
return "generic";
|
|
}
|
|
#endif
|
|
|
|
#if defined(__linux__) && defined(__arm__)
|
|
bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
|
std::string Err;
|
|
DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
|
|
if (!DS) {
|
|
DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
|
|
return false;
|
|
}
|
|
|
|
// Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
|
|
// in all cases.
|
|
char buffer[1024];
|
|
size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
|
|
delete DS;
|
|
|
|
StringRef Str(buffer, CPUInfoSize);
|
|
|
|
SmallVector<StringRef, 32> Lines;
|
|
Str.split(Lines, "\n");
|
|
|
|
SmallVector<StringRef, 32> CPUFeatures;
|
|
|
|
// Look for the CPU features.
|
|
for (unsigned I = 0, E = Lines.size(); I != E; ++I)
|
|
if (Lines[I].startswith("Features")) {
|
|
Lines[I].split(CPUFeatures, " ");
|
|
break;
|
|
}
|
|
|
|
for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
|
|
StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
|
|
.Case("half", "fp16")
|
|
.Case("neon", "neon")
|
|
.Case("vfpv3", "vfp3")
|
|
.Case("vfpv3d16", "d16")
|
|
.Case("vfpv4", "vfp4")
|
|
.Case("idiva", "hwdiv-arm")
|
|
.Case("idivt", "hwdiv")
|
|
.Default("");
|
|
|
|
if (LLVMFeatureStr != "")
|
|
Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
#else
|
|
bool sys::getHostCPUFeatures(StringMap<bool> &Features){
|
|
return false;
|
|
}
|
|
#endif
|
|
|
|
std::string sys::getProcessTriple() {
|
|
Triple PT(LLVM_HOST_TRIPLE);
|
|
|
|
if (sizeof(void *) == 8 && PT.isArch32Bit())
|
|
PT = PT.get64BitArchVariant();
|
|
if (sizeof(void *) == 4 && PT.isArch64Bit())
|
|
PT = PT.get32BitArchVariant();
|
|
|
|
return PT.str();
|
|
}
|