llvm-6502/test/CodeGen/Mips/align16.ll
Reed Kotler 6b9d461780 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 20:28:27 +00:00

31 lines
881 B
LLVM

; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=16
@i = global i32 25, align 4
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
define void @p(i32* %i) nounwind {
entry:
ret void
}
define void @foo() nounwind {
entry:
%y = alloca [512 x i32], align 4
%x = alloca i32, align 8
%zz = alloca i32, align 4
%z = alloca i32, align 4
%0 = load i32* @i, align 4
%arrayidx = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10
store i32 %0, i32* %arrayidx, align 4
%1 = load i32* @i, align 4
store i32 %1, i32* %x, align 8
call void @p(i32* %x)
%arrayidx1 = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10
call void @p(i32* %arrayidx1)
ret void
}
; 16: save $ra, $s0, $s1, 2040
; 16: addiu $sp, -48 # 16 bit inst
; 16: addiu $sp, 48 # 16 bit inst
; 16: restore $ra, $s0, $s1, 2040