mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-12 15:24:21 +00:00
d50bcb2162
This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
4.5 KiB
LLVM
174 lines
4.5 KiB
LLVM
; Test 32-bit atomic minimum and maximum.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check signed minium.
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define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f1:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: crjle %r2, %r4, [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jlh [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw min i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check signed maximum.
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define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f2:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: crjhe %r2, %r4, [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jlh [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw max i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check unsigned minimum.
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define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f3:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: clr %r2, %r4
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: jle [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jlh [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw umin i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check unsigned maximum.
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define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f4:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: clr %r2, %r4
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: jhe [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jlh [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw umax i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the aligned CS range.
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define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f5:
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; CHECK: l %r2, 4092(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1023
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word up, which requires CSY.
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define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f6:
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; CHECK: ly %r2, 4096(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1024
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the aligned CSY range.
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define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f7:
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; CHECK: ly %r2, 524284(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word up, which needs separate address logic.
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define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f8:
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; CHECK: agfi %r3, 524288
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the negative aligned CSY range.
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define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f9:
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; CHECK: ly %r2, -4(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the low end of the CSY range.
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define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f10:
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; CHECK: ly %r2, -524288(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word down, which needs separate address logic.
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define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK: f11:
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; CHECK: agfi %r3, -524292
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check that indexed addresses are not allowed.
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define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
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; CHECK: f12:
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; CHECK: agr %r3, %r4
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i32 *
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check that constants are forced into a register.
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define i32 @f13(i32 %dummy, i32 *%ptr) {
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; CHECK: f13:
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; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]]
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; CHECK: lr [[NEW]], [[LIMIT]]
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jlh [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw min i32 *%ptr, i32 42 seq_cst
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ret i32 %res
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}
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