mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b503b49b51
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
3.6 KiB
LLVM
132 lines
3.6 KiB
LLVM
; Test 32-bit compare and swap.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check the low end of the CS range.
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define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f1:
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; CHECK: cs %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check the high end of the aligned CS range.
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define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f2:
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; CHECK: cs %r2, %r3, 4092(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1023
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check the next word up, which should use CSY instead of CS.
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define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f3:
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; CHECK: csy %r2, %r3, 4096(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1024
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check the high end of the aligned CSY range.
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define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f4:
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; CHECK: csy %r2, %r3, 524284(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f5:
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; CHECK: agfi %r4, 524288
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; CHECK: cs %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check the high end of the negative aligned CSY range.
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define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f6:
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; CHECK: csy %r2, %r3, -4(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check the low end of the CSY range.
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define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f7:
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; CHECK: csy %r2, %r3, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
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; CHECK: f8:
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; CHECK: agfi %r4, -524292
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; CHECK: cs %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check that CS does not allow an index.
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define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
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; CHECK: f9:
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; CHECK: agr %r4, %r5
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; CHECK: cs %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%ptr = inttoptr i64 %add1 to i32 *
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check that CSY does not allow an index.
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define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
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; CHECK: f10:
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; CHECK: agr %r4, %r5
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; CHECK: csy %r2, %r3, 4096(%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i32 *
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst
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ret i32 %val
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}
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; Check that a constant %cmp value is loaded into a register first.
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define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
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; CHECK: f11:
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; CHECK: lhi %r2, 1001
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; CHECK: cs %r2, %r3, 0(%r4)
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; CHECK: br %r14
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%val = cmpxchg i32 *%ptr, i32 1001, i32 %swap seq_cst
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ret i32 %val
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}
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; Check that a constant %swap value is loaded into a register first.
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define i32 @f12(i32 %cmp, i32 *%ptr) {
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; CHECK: f12:
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; CHECK: lhi [[SWAP:%r[0-9]+]], 1002
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; CHECK: cs %r2, [[SWAP]], 0(%r3)
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; CHECK: br %r14
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%val = cmpxchg i32 *%ptr, i32 %cmp, i32 1002 seq_cst
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ret i32 %val
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}
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