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edfeeb6d70
The PowerPC backend, somewhat embarrassingly, did not generate an
optimal-length sequence of instructions for a 32-bit bswap. While adding a
pattern for the bswap intrinsic to fix this would not have been terribly
difficult, doing so would not have addressed the real problem: we had been
generating poor code for many bit-permuting operations (by which I mean things
like byte-swap that permute the bits of one or more inputs around in various
ways). Here are some initial steps toward solving this deficiency.
Bit-permuting operations are represented, at the SDAG level, using ISD::ROTL,
SHL, SRL, AND and OR (mostly with constant second operands). Looking back
through these operations, we can build up a description of the bits in the
resulting value in terms of bits of one or more input values (and constant
zeros). For each bit, we compute the rotation amount from the original value,
and then group consecutive (value, rotation factor) bits into groups. Groups
sharing these attributes are then collected and sorted, and we can then
instruction select the entire permutation using a combination of masked
rotations (rlwinm), imm ands (andi/andis), and masked rotation inserts
(rlwimi).
The result is that instead of lowering an i32 bswap as:
rlwinm 5, 3, 24, 16, 23
rlwinm 4, 3, 24, 0, 7
rlwimi 4, 3, 8, 8, 15
rlwimi 5, 3, 8, 24, 31
rlwimi 4, 5, 0, 16, 31
we now produce:
rlwinm 4, 3, 8, 0, 31
rlwimi 4, 3, 24, 16, 23
rlwimi 4, 3, 24, 0, 7
and for the 'test6' example in the PowerPC/README.txt file:
unsigned test6(unsigned x) {
return ((x & 0x00FF0000) >> 16) | ((x & 0x000000FF) << 16);
}
we used to produce:
lis 4, 255
rlwinm 3, 3, 16, 0, 31
ori 4, 4, 255
and 3, 3, 4
and now we produce:
rlwinm 4, 3, 16, 24, 31
rlwimi 4, 3, 16, 8, 15
and, as a nice bonus, this fixes the FIXME in
test/CodeGen/PowerPC/rlwimi-and.ll.
This commit does not include instruction-selection for i64 operations, those
will come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224318 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.4 KiB
LLVM
42 lines
1.4 KiB
LLVM
; RUN: llc -mcpu=pwr7 -mattr=-crbits < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-bgq-linux"
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define void @test() align 2 {
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entry:
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br i1 undef, label %codeRepl1, label %codeRepl31
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codeRepl1: ; preds = %entry
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br i1 undef, label %codeRepl4, label %codeRepl29
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codeRepl4: ; preds = %codeRepl1
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br i1 undef, label %codeRepl12, label %codeRepl17
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codeRepl12: ; preds = %codeRepl4
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unreachable
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codeRepl17: ; preds = %codeRepl4
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%0 = load i8* undef, align 2
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%1 = and i8 %0, 1
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%not.tobool.i.i.i = icmp eq i8 %1, 0
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%2 = select i1 %not.tobool.i.i.i, i16 0, i16 256
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%3 = load i8* undef, align 1
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%4 = and i8 %3, 1
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%not.tobool.i.1.i.i = icmp eq i8 %4, 0
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%rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1
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%rvml38.sroa.0.0.insert.insert = or i16 %rvml38.sroa.1.1.insert.ext, %2
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store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2
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unreachable
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; CHECK: @test
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; CHECK: rlwinm [[R1:[0-9]+]], {{[0-9]+}}, 0, 31, 31
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; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23
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codeRepl29: ; preds = %codeRepl1
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unreachable
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codeRepl31: ; preds = %entry
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ret void
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}
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