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https://github.com/c64scene-ar/llvm-6502.git
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c2ecf3efbf
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix about instructions with partial register updates causing false unwanted dependencies. The ExecutionDepsFix pass will break the false dependencies if the updated register was written in the previoius N instructions. The small loop added to sse-domains.ll runs twice as fast with dependency-breaking instructions inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
3.2 KiB
LLVM
87 lines
3.2 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.7"
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; CHECK: f
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;
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; This function contains load / store / and operations that all can execute in
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; any domain. The only domain-specific operation is the %add = shl... operation
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; which is <4 x i32>.
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;
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; The paddd instruction can only influence the other operations through the loop
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; back-edge. Check that everything is still moved into the integer domain.
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define void @f(<4 x i32>* nocapture %p, i32 %n) nounwind uwtable ssp {
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entry:
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br label %while.body
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; Materialize a zeroinitializer and a constant-pool load in the integer domain.
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; The order is not important.
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; CHECK: pxor
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; CHECK: movdqa
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; The instructions in the loop must all be integer domain as well.
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; CHECK: while.body
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; CHECK: pand
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; CHECK: movdqa
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; CHECK: movdqa
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; Finally, the controlling integer-only instruction.
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; CHECK: paddd
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while.body:
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%p.addr.04 = phi <4 x i32>* [ %incdec.ptr, %while.body ], [ %p, %entry ]
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%n.addr.03 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
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%x.02 = phi <4 x i32> [ %add, %while.body ], [ zeroinitializer, %entry ]
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%dec = add nsw i32 %n.addr.03, -1
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%and = and <4 x i32> %x.02, <i32 127, i32 127, i32 127, i32 127>
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%incdec.ptr = getelementptr inbounds <4 x i32>* %p.addr.04, i64 1
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store <4 x i32> %and, <4 x i32>* %p.addr.04, align 16
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%0 = load <4 x i32>* %incdec.ptr, align 16
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%add = shl <4 x i32> %0, <i32 1, i32 1, i32 1, i32 1>
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end:
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ret void
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}
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; CHECK: f2
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;
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; This loop contains two cvtsi2ss instructions that update the same xmm
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; register. Verify that the execution dependency fix pass breaks those
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; dependencies by inserting xorps instructions.
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;
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; If the register allocator chooses different registers for the two cvtsi2ss
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; instructions, they are still dependent on themselves.
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; CHECK: xorps [[XMM1:%xmm[0-9]+]]
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; CHECK: , [[XMM1]]
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; CHECK: cvtsi2ss %{{.*}}, [[XMM1]]
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; CHECK: xorps [[XMM2:%xmm[0-9]+]]
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; CHECK: , [[XMM2]]
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; CHECK: cvtsi2ss %{{.*}}, [[XMM2]]
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;
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define float @f2(i32 %m) nounwind uwtable readnone ssp {
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entry:
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%tobool3 = icmp eq i32 %m, 0
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br i1 %tobool3, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body
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%m.addr.07 = phi i32 [ %dec, %for.body ], [ %m, %entry ]
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%s1.06 = phi float [ %add, %for.body ], [ 0.000000e+00, %entry ]
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%s2.05 = phi float [ %add2, %for.body ], [ 0.000000e+00, %entry ]
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%n.04 = phi i32 [ %inc, %for.body ], [ 1, %entry ]
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%conv = sitofp i32 %n.04 to float
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%add = fadd float %s1.06, %conv
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%conv1 = sitofp i32 %m.addr.07 to float
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%add2 = fadd float %s2.05, %conv1
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%inc = add nsw i32 %n.04, 1
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%dec = add nsw i32 %m.addr.07, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%s1.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
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%s2.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add2, %for.body ]
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%sub = fsub float %s1.0.lcssa, %s2.0.lcssa
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ret float %sub
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}
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