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https://github.com/c64scene-ar/llvm-6502.git
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f6372aa1cc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
185 lines
7.0 KiB
C++
185 lines
7.0 KiB
C++
//===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the IA64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "IA64InstrInfo.h"
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#include "IA64.h"
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#include "IA64InstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "IA64GenInstrInfo.inc"
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using namespace llvm;
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IA64InstrInfo::IA64InstrInfo()
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: TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
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RI(*this) {
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}
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bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == IA64::MOV || oc == IA64::FMOV) {
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// TODO: this doesn't detect predicate moves
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assert(MI.getNumOperands() >= 2 &&
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/* MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() && */
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"invalid register-register move instruction");
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if( MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() ) {
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// if both operands of the MOV/FMOV are registers, then
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// yes, this is a move instruction
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
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// move instruction
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}
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unsigned
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IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond)const {
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
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return 1;
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}
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void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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cerr << "Not yet supported!";
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abort();
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}
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if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
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// (SrcReg) DestReg = cmp.eq.unc(r0, r0)
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BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg)
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.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
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else // otherwise, MOV works (for both gen. regs and FP regs)
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BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
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}
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void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIdx,
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const TargetRegisterClass *RC) const{
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if (RC == IA64::FPRegisterClass) {
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BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
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.addReg(SrcReg, false, false, isKill);
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} else if (RC == IA64::GRRegisterClass) {
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BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx)
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.addReg(SrcReg, false, false, isKill);
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} else if (RC == IA64::PRRegisterClass) {
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/* we use IA64::r2 as a temporary register for doing this hackery. */
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// first we load 0:
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BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
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// then conditionally add 1:
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BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
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.addImm(1).addReg(SrcReg, false, false, isKill);
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// and then store it to the stack
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BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
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} else assert(0 &&
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"sorry, I don't know how to store this sort of reg in the stack\n");
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}
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void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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unsigned Opc = 0;
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if (RC == IA64::FPRegisterClass) {
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Opc = IA64::STF8;
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} else if (RC == IA64::GRRegisterClass) {
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Opc = IA64::ST8;
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} else if (RC == IA64::PRRegisterClass) {
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Opc = IA64::ST1;
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} else {
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assert(0 &&
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"sorry, I don't know how to store this sort of reg\n");
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}
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MachineInstrBuilder MIB = BuildMI(get(Opc));
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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MIB.addReg(SrcReg, false, false, isKill);
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NewMIs.push_back(MIB);
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return;
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}
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void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC)const{
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if (RC == IA64::FPRegisterClass) {
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BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
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} else if (RC == IA64::GRRegisterClass) {
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BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
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} else if (RC == IA64::PRRegisterClass) {
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// first we load a byte from the stack into r2, our 'predicate hackery'
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// scratch reg
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BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
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// then we compare it to zero. If it _is_ zero, compare-not-equal to
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// r0 gives us 0, which is what we want, so that's nice.
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BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
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} else assert(0 &&
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"sorry, I don't know how to load this sort of reg from the stack\n");
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}
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void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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unsigned Opc = 0;
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if (RC == IA64::FPRegisterClass) {
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Opc = IA64::LDF8;
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} else if (RC == IA64::GRRegisterClass) {
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Opc = IA64::LD8;
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} else if (RC == IA64::PRRegisterClass) {
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Opc = IA64::LD1;
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} else {
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assert(0 &&
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"sorry, I don't know how to store this sort of reg\n");
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}
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MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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NewMIs.push_back(MIB);
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return;
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}
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