mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
4.3 KiB
LLVM
117 lines
4.3 KiB
LLVM
; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
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define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
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; CHECK-LABEL: vector_ext_2i8_to_2i64:
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; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
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; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xff
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; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
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; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
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; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
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; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
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; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
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; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
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; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
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; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
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; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
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; CHECK-NEXT: bx lr
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%1 = load <2 x i8>, <2 x i8>* %loadaddr
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%2 = zext <2 x i8> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %storeaddr
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ret void
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}
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define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
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; CHECK-LABEL: vector_ext_2i16_to_2i64:
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; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
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; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xffff
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; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
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; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
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; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
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; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
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; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
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; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
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; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
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; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
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; CHECK-NEXT: bx lr
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%1 = load <2 x i16>, <2 x i16>* %loadaddr
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%2 = zext <2 x i16> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %storeaddr
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ret void
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}
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define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
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; CHECK-LABEL: vector_ext_2i8_to_2i32:
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; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
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; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
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; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
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; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
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; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
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; CHECK-NEXT: vstr [[REG]], [r1]
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; CHECK-NEXT: bx lr
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%1 = load <2 x i8>, <2 x i8>* %loadaddr
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%2 = zext <2 x i8> %1 to <2 x i32>
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store <2 x i32> %2, <2 x i32>* %storeaddr
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ret void
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}
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define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
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; CHECK-LABEL: vector_ext_2i16_to_2i32:
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; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
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; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
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; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
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; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
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; CHECK-NEXT: vstr [[REG]], [r1]
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; CHECK-NEXT: bx lr
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%1 = load <2 x i16>, <2 x i16>* %loadaddr
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%2 = zext <2 x i16> %1 to <2 x i32>
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store <2 x i32> %2, <2 x i32>* %storeaddr
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ret void
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}
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define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
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; CHECK-LABEL: vector_ext_2i8_to_2i16:
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; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
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; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
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; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
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; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
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; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
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; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}
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; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
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; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
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; CHECK-NEXT: bx lr
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%1 = load <2 x i8>, <2 x i8>* %loadaddr
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%2 = zext <2 x i8> %1 to <2 x i16>
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store <2 x i16> %2, <2 x i16>* %storeaddr
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ret void
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}
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define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) {
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; CHECK-LABEL: vector_ext_4i8_to_4i32:
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; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
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; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
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; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
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; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
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; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
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; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
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; CHECK-NEXT: bx lr
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%1 = load <4 x i8>, <4 x i8>* %loadaddr
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%2 = zext <4 x i8> %1 to <4 x i32>
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store <4 x i32> %2, <4 x i32>* %storeaddr
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ret void
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}
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define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) {
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; CHECK-LABEL: vector_ext_4i8_to_4i16:
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; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
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; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
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; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
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; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
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; CHECK-NEXT: vstr [[REG]], [r1]
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; CHECK-NEXT: bx lr
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%1 = load <4 x i8>, <4 x i8>* %loadaddr
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%2 = zext <4 x i8> %1 to <4 x i16>
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store <4 x i16> %2, <4 x i16>* %storeaddr
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ret void
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}
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