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https://github.com/c64scene-ar/llvm-6502.git
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65de504ad2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92591 91177308-0d34-0410-b5e6-96231b3b80d8
528 lines
20 KiB
C++
528 lines
20 KiB
C++
//===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "spiller"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <set>
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using namespace llvm;
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namespace {
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enum SpillerName { trivial, standard, splitting };
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}
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static cl::opt<SpillerName>
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spillerOpt("spiller",
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cl::desc("Spiller to use: (default: standard)"),
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cl::Prefix,
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cl::values(clEnumVal(trivial, "trivial spiller"),
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clEnumVal(standard, "default spiller"),
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clEnumVal(splitting, "splitting spiller"),
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clEnumValEnd),
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cl::init(standard));
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// Spiller virtual destructor implementation.
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Spiller::~Spiller() {}
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namespace {
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/// Utility class for spillers.
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class SpillerBase : public Spiller {
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protected:
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MachineFunction *mf;
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LiveIntervals *lis;
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MachineFrameInfo *mfi;
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MachineRegisterInfo *mri;
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const TargetInstrInfo *tii;
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VirtRegMap *vrm;
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/// Construct a spiller base.
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SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
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: mf(mf), lis(lis), vrm(vrm)
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{
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mfi = mf->getFrameInfo();
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mri = &mf->getRegInfo();
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tii = mf->getTarget().getInstrInfo();
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}
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/// Add spill ranges for every use/def of the live interval, inserting loads
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/// immediately before each use, and stores after each def. No folding or
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/// remat is attempted.
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std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
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DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
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assert(li->weight != HUGE_VALF &&
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"Attempting to spill already spilled value.");
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assert(!li->isStackSlot() &&
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"Trying to spill a stack slot.");
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DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
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std::vector<LiveInterval*> added;
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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unsigned ss = vrm->assignVirt2StackSlot(li->reg);
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// Iterate over reg uses/defs.
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for (MachineRegisterInfo::reg_iterator
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regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
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// Grab the use/def instr.
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MachineInstr *mi = &*regItr;
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DEBUG(dbgs() << " Processing " << *mi);
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// Step regItr to the next use/def instr.
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do {
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++regItr;
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} while (regItr != mri->reg_end() && (&*regItr == mi));
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// Collect uses & defs for this instr.
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SmallVector<unsigned, 2> indices;
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bool hasUse = false;
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bool hasDef = false;
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for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
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MachineOperand &op = mi->getOperand(i);
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if (!op.isReg() || op.getReg() != li->reg)
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continue;
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hasUse |= mi->getOperand(i).isUse();
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hasDef |= mi->getOperand(i).isDef();
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indices.push_back(i);
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}
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// Create a new vreg & interval for this instr.
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unsigned newVReg = mri->createVirtualRegister(trc);
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vrm->grow();
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vrm->assignVirt2StackSlot(newVReg, ss);
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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newLI->weight = HUGE_VALF;
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// Update the reg operands & kill flags.
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for (unsigned i = 0; i < indices.size(); ++i) {
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unsigned mopIdx = indices[i];
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MachineOperand &mop = mi->getOperand(mopIdx);
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mop.setReg(newVReg);
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if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
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mop.setIsKill(true);
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}
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}
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assert(hasUse || hasDef);
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// Insert reload if necessary.
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MachineBasicBlock::iterator miItr(mi);
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if (hasUse) {
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tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc);
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MachineInstr *loadInstr(prior(miItr));
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SlotIndex loadIndex =
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lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
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SlotIndex endIndex = loadIndex.getNextIndex();
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VNInfo *loadVNI =
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newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
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loadVNI->addKill(endIndex);
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newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
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}
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// Insert store if necessary.
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if (hasDef) {
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tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg, true,
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ss, trc);
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MachineInstr *storeInstr(llvm::next(miItr));
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SlotIndex storeIndex =
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lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
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SlotIndex beginIndex = storeIndex.getPrevIndex();
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VNInfo *storeVNI =
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newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());
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storeVNI->addKill(storeIndex);
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newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
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}
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added.push_back(newLI);
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}
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return added;
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}
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};
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/// Spills any live range using the spill-everywhere method with no attempt at
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/// folding.
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class TrivialSpiller : public SpillerBase {
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public:
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TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
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: SpillerBase(mf, lis, vrm) {}
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std::vector<LiveInterval*> spill(LiveInterval *li,
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SmallVectorImpl<LiveInterval*> &spillIs,
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SlotIndex*) {
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// Ignore spillIs - we don't use it.
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return trivialSpillEverywhere(li);
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}
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};
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/// Falls back on LiveIntervals::addIntervalsForSpills.
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class StandardSpiller : public Spiller {
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protected:
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LiveIntervals *lis;
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const MachineLoopInfo *loopInfo;
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VirtRegMap *vrm;
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public:
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StandardSpiller(LiveIntervals *lis, const MachineLoopInfo *loopInfo,
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VirtRegMap *vrm)
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: lis(lis), loopInfo(loopInfo), vrm(vrm) {}
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/// Falls back on LiveIntervals::addIntervalsForSpills.
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std::vector<LiveInterval*> spill(LiveInterval *li,
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SmallVectorImpl<LiveInterval*> &spillIs,
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SlotIndex*) {
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return lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
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}
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};
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/// When a call to spill is placed this spiller will first try to break the
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/// interval up into its component values (one new interval per value).
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/// If this fails, or if a call is placed to spill a previously split interval
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/// then the spiller falls back on the standard spilling mechanism.
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class SplittingSpiller : public StandardSpiller {
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public:
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SplittingSpiller(MachineFunction *mf, LiveIntervals *lis,
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const MachineLoopInfo *loopInfo, VirtRegMap *vrm)
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: StandardSpiller(lis, loopInfo, vrm) {
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mri = &mf->getRegInfo();
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tii = mf->getTarget().getInstrInfo();
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tri = mf->getTarget().getRegisterInfo();
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}
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std::vector<LiveInterval*> spill(LiveInterval *li,
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SmallVectorImpl<LiveInterval*> &spillIs,
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SlotIndex *earliestStart) {
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if (worthTryingToSplit(li)) {
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return tryVNISplit(li, earliestStart);
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}
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// else
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return StandardSpiller::spill(li, spillIs, earliestStart);
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}
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private:
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MachineRegisterInfo *mri;
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const TargetInstrInfo *tii;
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const TargetRegisterInfo *tri;
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DenseSet<LiveInterval*> alreadySplit;
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bool worthTryingToSplit(LiveInterval *li) const {
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return (!alreadySplit.count(li) && li->getNumValNums() > 1);
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}
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/// Try to break a LiveInterval into its component values.
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std::vector<LiveInterval*> tryVNISplit(LiveInterval *li,
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SlotIndex *earliestStart) {
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DEBUG(dbgs() << "Trying VNI split of %reg" << *li << "\n");
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std::vector<LiveInterval*> added;
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SmallVector<VNInfo*, 4> vnis;
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std::copy(li->vni_begin(), li->vni_end(), std::back_inserter(vnis));
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for (SmallVectorImpl<VNInfo*>::iterator vniItr = vnis.begin(),
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vniEnd = vnis.end(); vniItr != vniEnd; ++vniItr) {
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VNInfo *vni = *vniItr;
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// Skip unused VNIs, or VNIs with no kills.
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if (vni->isUnused() || vni->kills.empty())
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continue;
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DEBUG(dbgs() << " Extracted Val #" << vni->id << " as ");
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LiveInterval *splitInterval = extractVNI(li, vni);
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if (splitInterval != 0) {
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DEBUG(dbgs() << *splitInterval << "\n");
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added.push_back(splitInterval);
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alreadySplit.insert(splitInterval);
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if (earliestStart != 0) {
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if (splitInterval->beginIndex() < *earliestStart)
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*earliestStart = splitInterval->beginIndex();
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}
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} else {
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DEBUG(dbgs() << "0\n");
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}
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}
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DEBUG(dbgs() << "Original LI: " << *li << "\n");
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// If there original interval still contains some live ranges
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// add it to added and alreadySplit.
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if (!li->empty()) {
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added.push_back(li);
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alreadySplit.insert(li);
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if (earliestStart != 0) {
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if (li->beginIndex() < *earliestStart)
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*earliestStart = li->beginIndex();
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}
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}
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return added;
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}
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/// Extract the given value number from the interval.
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LiveInterval* extractVNI(LiveInterval *li, VNInfo *vni) const {
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assert(vni->isDefAccurate() || vni->isPHIDef());
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assert(!vni->kills.empty());
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// Create a new vreg and live interval, copy VNI kills & ranges over.
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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unsigned newVReg = mri->createVirtualRegister(trc);
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vrm->grow();
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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VNInfo *newVNI = newLI->createValueCopy(vni, lis->getVNInfoAllocator());
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// Start by copying all live ranges in the VN to the new interval.
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for (LiveInterval::iterator rItr = li->begin(), rEnd = li->end();
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rItr != rEnd; ++rItr) {
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if (rItr->valno == vni) {
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newLI->addRange(LiveRange(rItr->start, rItr->end, newVNI));
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}
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}
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// Erase the old VNI & ranges.
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li->removeValNo(vni);
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// Collect all current uses of the register belonging to the given VNI.
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// We'll use this to rename the register after we've dealt with the def.
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std::set<MachineInstr*> uses;
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for (MachineRegisterInfo::use_iterator
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useItr = mri->use_begin(li->reg), useEnd = mri->use_end();
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useItr != useEnd; ++useItr) {
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uses.insert(&*useItr);
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}
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// Process the def instruction for this VNI.
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if (newVNI->isPHIDef()) {
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// Insert a copy at the start of the MBB. The range proceeding the
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// copy will be attached to the original LiveInterval.
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MachineBasicBlock *defMBB = lis->getMBBFromIndex(newVNI->def);
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tii->copyRegToReg(*defMBB, defMBB->begin(), newVReg, li->reg, trc, trc);
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MachineInstr *copyMI = defMBB->begin();
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copyMI->addRegisterKilled(li->reg, tri);
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SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
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VNInfo *phiDefVNI = li->getNextValue(lis->getMBBStartIdx(defMBB),
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0, false, lis->getVNInfoAllocator());
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phiDefVNI->setIsPHIDef(true);
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phiDefVNI->addKill(copyIdx.getDefIndex());
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li->addRange(LiveRange(phiDefVNI->def, copyIdx.getDefIndex(), phiDefVNI));
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LiveRange *oldPHIDefRange =
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newLI->getLiveRangeContaining(lis->getMBBStartIdx(defMBB));
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// If the old phi def starts in the middle of the range chop it up.
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if (oldPHIDefRange->start < lis->getMBBStartIdx(defMBB)) {
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LiveRange oldPHIDefRange2(copyIdx.getDefIndex(), oldPHIDefRange->end,
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oldPHIDefRange->valno);
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oldPHIDefRange->end = lis->getMBBStartIdx(defMBB);
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newLI->addRange(oldPHIDefRange2);
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} else if (oldPHIDefRange->start == lis->getMBBStartIdx(defMBB)) {
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// Otherwise if it's at the start of the range just trim it.
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oldPHIDefRange->start = copyIdx.getDefIndex();
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} else {
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assert(false && "PHI def range doesn't cover PHI def?");
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}
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newVNI->def = copyIdx.getDefIndex();
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newVNI->setCopy(copyMI);
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newVNI->setIsPHIDef(false); // not a PHI def anymore.
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newVNI->setIsDefAccurate(true);
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} else {
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// non-PHI def. Rename the def. If it's two-addr that means renaming the use
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// and inserting a new copy too.
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MachineInstr *defInst = lis->getInstructionFromIndex(newVNI->def);
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// We'll rename this now, so we can remove it from uses.
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uses.erase(defInst);
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unsigned defOpIdx = defInst->findRegisterDefOperandIdx(li->reg);
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bool isTwoAddr = defInst->isRegTiedToUseOperand(defOpIdx),
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twoAddrUseIsUndef = false;
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for (unsigned i = 0; i < defInst->getNumOperands(); ++i) {
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MachineOperand &mo = defInst->getOperand(i);
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if (mo.isReg() && (mo.isDef() || isTwoAddr) && (mo.getReg()==li->reg)) {
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mo.setReg(newVReg);
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if (isTwoAddr && mo.isUse() && mo.isUndef())
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twoAddrUseIsUndef = true;
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}
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}
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SlotIndex defIdx = lis->getInstructionIndex(defInst);
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newVNI->def = defIdx.getDefIndex();
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if (isTwoAddr && !twoAddrUseIsUndef) {
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MachineBasicBlock *defMBB = defInst->getParent();
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tii->copyRegToReg(*defMBB, defInst, newVReg, li->reg, trc, trc);
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MachineInstr *copyMI = prior(MachineBasicBlock::iterator(defInst));
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SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
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copyMI->addRegisterKilled(li->reg, tri);
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LiveRange *origUseRange =
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li->getLiveRangeContaining(newVNI->def.getUseIndex());
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VNInfo *origUseVNI = origUseRange->valno;
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origUseRange->end = copyIdx.getDefIndex();
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bool updatedKills = false;
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for (unsigned k = 0; k < origUseVNI->kills.size(); ++k) {
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if (origUseVNI->kills[k] == defIdx.getDefIndex()) {
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origUseVNI->kills[k] = copyIdx.getDefIndex();
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updatedKills = true;
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break;
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}
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}
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assert(updatedKills && "Failed to update VNI kill list.");
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VNInfo *copyVNI = newLI->getNextValue(copyIdx.getDefIndex(), copyMI,
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true, lis->getVNInfoAllocator());
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copyVNI->addKill(defIdx.getDefIndex());
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LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI);
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newLI->addRange(copyRange);
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}
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}
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for (std::set<MachineInstr*>::iterator
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usesItr = uses.begin(), usesEnd = uses.end();
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usesItr != usesEnd; ++usesItr) {
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MachineInstr *useInst = *usesItr;
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SlotIndex useIdx = lis->getInstructionIndex(useInst);
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LiveRange *useRange =
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newLI->getLiveRangeContaining(useIdx.getUseIndex());
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// If this use doesn't belong to the new interval skip it.
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if (useRange == 0)
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continue;
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// This use doesn't belong to the VNI, skip it.
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if (useRange->valno != newVNI)
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continue;
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// Check if this instr is two address.
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unsigned useOpIdx = useInst->findRegisterUseOperandIdx(li->reg);
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bool isTwoAddress = useInst->isRegTiedToDefOperand(useOpIdx);
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// Rename uses (and defs for two-address instrs).
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for (unsigned i = 0; i < useInst->getNumOperands(); ++i) {
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MachineOperand &mo = useInst->getOperand(i);
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if (mo.isReg() && (mo.isUse() || isTwoAddress) &&
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(mo.getReg() == li->reg)) {
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mo.setReg(newVReg);
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}
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}
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// If this is a two address instruction we've got some extra work to do.
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if (isTwoAddress) {
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// We modified the def operand, so we need to copy back to the original
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// reg.
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MachineBasicBlock *useMBB = useInst->getParent();
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MachineBasicBlock::iterator useItr(useInst);
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tii->copyRegToReg(*useMBB, next(useItr), li->reg, newVReg, trc, trc);
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MachineInstr *copyMI = next(useItr);
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copyMI->addRegisterKilled(newVReg, tri);
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SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
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// Change the old two-address defined range & vni to start at
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// (and be defined by) the copy.
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LiveRange *origDefRange =
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li->getLiveRangeContaining(useIdx.getDefIndex());
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origDefRange->start = copyIdx.getDefIndex();
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origDefRange->valno->def = copyIdx.getDefIndex();
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origDefRange->valno->setCopy(copyMI);
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// Insert a new range & vni for the two-address-to-copy value. This
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// will be attached to the new live interval.
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VNInfo *copyVNI =
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newLI->getNextValue(useIdx.getDefIndex(), 0, true,
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lis->getVNInfoAllocator());
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copyVNI->addKill(copyIdx.getDefIndex());
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LiveRange copyRange(useIdx.getDefIndex(),copyIdx.getDefIndex(),copyVNI);
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newLI->addRange(copyRange);
|
|
}
|
|
}
|
|
|
|
// Iterate over any PHI kills - we'll need to insert new copies for them.
|
|
for (VNInfo::KillSet::iterator
|
|
killItr = newVNI->kills.begin(), killEnd = newVNI->kills.end();
|
|
killItr != killEnd; ++killItr) {
|
|
SlotIndex killIdx(*killItr);
|
|
if (killItr->isPHI()) {
|
|
MachineBasicBlock *killMBB = lis->getMBBFromIndex(killIdx);
|
|
LiveRange *oldKillRange =
|
|
newLI->getLiveRangeContaining(killIdx);
|
|
|
|
assert(oldKillRange != 0 && "No kill range?");
|
|
|
|
tii->copyRegToReg(*killMBB, killMBB->getFirstTerminator(),
|
|
li->reg, newVReg, trc, trc);
|
|
MachineInstr *copyMI = prior(killMBB->getFirstTerminator());
|
|
copyMI->addRegisterKilled(newVReg, tri);
|
|
SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
|
|
|
|
// Save the current end. We may need it to add a new range if the
|
|
// current range runs of the end of the MBB.
|
|
SlotIndex newKillRangeEnd = oldKillRange->end;
|
|
oldKillRange->end = copyIdx.getDefIndex();
|
|
|
|
if (newKillRangeEnd != lis->getMBBEndIdx(killMBB)) {
|
|
assert(newKillRangeEnd > lis->getMBBEndIdx(killMBB) &&
|
|
"PHI kill range doesn't reach kill-block end. Not sane.");
|
|
newLI->addRange(LiveRange(lis->getMBBEndIdx(killMBB),
|
|
newKillRangeEnd, newVNI));
|
|
}
|
|
|
|
*killItr = oldKillRange->end;
|
|
VNInfo *newKillVNI = li->getNextValue(copyIdx.getDefIndex(),
|
|
copyMI, true,
|
|
lis->getVNInfoAllocator());
|
|
newKillVNI->addKill(lis->getMBBTerminatorGap(killMBB));
|
|
newKillVNI->setHasPHIKill(true);
|
|
li->addRange(LiveRange(copyIdx.getDefIndex(),
|
|
lis->getMBBEndIdx(killMBB),
|
|
newKillVNI));
|
|
}
|
|
|
|
}
|
|
|
|
newVNI->setHasPHIKill(false);
|
|
|
|
return newLI;
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
|
|
const MachineLoopInfo *loopInfo,
|
|
VirtRegMap *vrm) {
|
|
switch (spillerOpt) {
|
|
case trivial: return new TrivialSpiller(mf, lis, vrm); break;
|
|
case standard: return new StandardSpiller(lis, loopInfo, vrm); break;
|
|
case splitting: return new SplittingSpiller(mf, lis, loopInfo, vrm); break;
|
|
default: llvm_unreachable("Unreachable!"); break;
|
|
}
|
|
}
|