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https://github.com/c64scene-ar/llvm-6502.git
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c3f16b316a
-Fix binary codes and rename operands in .td files so that automatically generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct encoding for instructions. -Define new class FMem for instructions that access memory. -Define new class FFRGPR for instructions that move data between GPR and FPU general and control registers. -Define custom encoder methods for memory operands, and also for size operands of ext and ins instructions. -Only static relocation model is currently implemented. Patch by Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142378 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
748 B
Makefile
24 lines
748 B
Makefile
##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = LLVMMipsCodeGen
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TARGET = Mips
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
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MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
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MipsGenDAGISel.inc MipsGenCallingConv.inc \
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MipsGenSubtargetInfo.inc
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DIRS = InstPrinter TargetInfo MCTargetDesc
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include $(LEVEL)/Makefile.common
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