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This patch allows SSE4.1 targets to use (V)PINSRB to create 16i8 vectors by inserting i8 scalars directly into a XMM register instead of merging pairs of i8 scalars into a i16 and using the SSE2 PINSRW instruction. This allows folding of byte loads and reduces scalar register usage as well. Differential Revision: http://reviews.llvm.org/D8839 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234193 91177308-0d34-0410-b5e6-96231b3b80d8 |
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AArch64 | ||
ARM | ||
BPF | ||
CPP | ||
Generic | ||
Hexagon | ||
Inputs | ||
Mips | ||
MSP430 | ||
NVPTX | ||
PowerPC | ||
R600 | ||
SPARC | ||
SystemZ | ||
Thumb | ||
Thumb2 | ||
WinEH | ||
X86 | ||
XCore |