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20b0abc24f
long live interval that has low usage density. 1. Change order of coalescing to join physical registers with virtual registers first before virtual register intervals become too long. 2. Check size and usage density to determine if it's worthwhile to join. 3. If joining is aborted, assign virtual register live interval allocation preference field to the physical register. 4. Register allocator should try to allocate to the preferred register first (if available) to create identify moves that can be eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36218 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
AsmPrinter.h | ||
CallingConvLower.h | ||
DwarfWriter.h | ||
FileWriters.h | ||
InstrScheduling.h | ||
IntrinsicLowering.h | ||
LinkAllCodegenComponents.h | ||
LiveInterval.h | ||
LiveIntervalAnalysis.h | ||
LiveVariables.h | ||
MachineBasicBlock.h | ||
MachineCodeEmitter.h | ||
MachineConstantPool.h | ||
MachineFrameInfo.h | ||
MachineFunction.h | ||
MachineFunctionPass.h | ||
MachineInstr.h | ||
MachineInstrBuilder.h | ||
MachineJumpTableInfo.h | ||
MachineLocation.h | ||
MachineModuleInfo.h | ||
MachinePassRegistry.h | ||
MachineRelocation.h | ||
MachORelocation.h | ||
Passes.h | ||
RegAllocRegistry.h | ||
RegisterScavenging.h | ||
RuntimeLibcalls.h | ||
SchedGraphCommon.h | ||
ScheduleDAG.h | ||
SchedulerRegistry.h | ||
SelectionDAG.h | ||
SelectionDAGISel.h | ||
SelectionDAGNodes.h | ||
SSARegMap.h | ||
ValueTypes.h | ||
ValueTypes.td |