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The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
3.9 KiB
C++
86 lines
3.9 KiB
C++
//===- MBlaze.td - Describe the MBlaze Target Machine -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the MBlaze target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "MBlazeRegisterInfo.td"
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include "MBlazeSchedule.td"
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include "MBlazeIntrinsics.td"
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include "MBlazeInstrInfo.td"
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include "MBlazeCallingConv.td"
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def MBlazeInstrInfo : InstrInfo {
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let TSFlagsFields = [];
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let TSFlagsShifts = [];
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}
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//===----------------------------------------------------------------------===//
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// Microblaze Subtarget features //
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//===----------------------------------------------------------------------===//
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def FeaturePipe3 : SubtargetFeature<"pipe3", "HasPipe3", "true",
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"Implements 3-stage pipeline.">;
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def FeatureBarrel : SubtargetFeature<"barrel", "HasBarrel", "true",
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"Implements barrel shifter.">;
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def FeatureDiv : SubtargetFeature<"div", "HasDiv", "true",
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"Implements hardware divider.">;
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def FeatureMul : SubtargetFeature<"mul", "HasMul", "true",
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"Implements hardware multiplier.">;
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def FeatureFSL : SubtargetFeature<"fsl", "HasFSL", "true",
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"Implements FSL instructions.">;
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def FeatureEFSL : SubtargetFeature<"efsl", "HasEFSL", "true",
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"Implements extended FSL instructions.">;
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def FeatureMSRSet : SubtargetFeature<"msrset", "HasMSRSet", "true",
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"Implements MSR register set and clear.">;
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def FeatureException : SubtargetFeature<"exception", "HasException", "true",
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"Implements hardware exception support.">;
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def FeaturePatCmp : SubtargetFeature<"patcmp", "HasPatCmp", "true",
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"Implements pattern compare instruction.">;
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def FeatureFPU : SubtargetFeature<"fpu", "HasFPU", "true",
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"Implements floating point unit.">;
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def FeatureESR : SubtargetFeature<"esr", "HasESR", "true",
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"Implements ESR and EAR registers">;
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def FeaturePVR : SubtargetFeature<"pvr", "HasPVR", "true",
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"Implements processor version register.">;
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def FeatureMul64 : SubtargetFeature<"mul64", "HasMul64", "true",
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"Implements multiplier with 64-bit result">;
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def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true",
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"Implements sqrt and floating point convert.">;
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def FeatureMMU : SubtargetFeature<"mmu", "HasMMU", "true",
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"Implements memory management unit.">;
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//===----------------------------------------------------------------------===//
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// MBlaze processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MBlazeGenericItineraries, Features>;
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def : Proc<"v400", []>;
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def : Proc<"v500", []>;
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def : Proc<"v600", []>;
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def : Proc<"v700", []>;
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def : Proc<"v710", []>;
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def MBlaze : Target {
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let InstructionSet = MBlazeInstrInfo;
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}
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