mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
1.6 KiB
LLVM
72 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
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define ptx_device i16 @t1_u16(i16 %x, i16 %y) {
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; CHECK: add.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, rh{{[0-9]+}};
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; CHECK-NEXT: ret;
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%z = add i16 %x, %y
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ret i16 %z
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}
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define ptx_device i32 @t1_u32(i32 %x, i32 %y) {
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; CHECK: add.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: ret;
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%z = add i32 %x, %y
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ret i32 %z
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}
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define ptx_device i64 @t1_u64(i64 %x, i64 %y) {
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; CHECK: add.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
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; CHECK-NEXT: ret;
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%z = add i64 %x, %y
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ret i64 %z
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}
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define ptx_device float @t1_f32(float %x, float %y) {
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; CHECK: add.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
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; CHECK-NEXT: ret;
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%z = fadd float %x, %y
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ret float %z
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}
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define ptx_device double @t1_f64(double %x, double %y) {
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; CHECK: add.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}
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; CHECK-NEXT: ret;
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%z = fadd double %x, %y
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ret double %z
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}
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define ptx_device i16 @t2_u16(i16 %x) {
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; CHECK: add.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, 1;
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; CHECK-NEXT: ret;
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%z = add i16 %x, 1
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ret i16 %z
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}
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define ptx_device i32 @t2_u32(i32 %x) {
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; CHECK: add.u32 r{{[0-9]+}}, r{{[0-9]+}}, 1;
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; CHECK-NEXT: ret;
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%z = add i32 %x, 1
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ret i32 %z
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}
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define ptx_device i64 @t2_u64(i64 %x) {
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; CHECK: add.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, 1;
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; CHECK-NEXT: ret;
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%z = add i64 %x, 1
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ret i64 %z
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}
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define ptx_device float @t2_f32(float %x) {
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; CHECK: add.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, 0F3F800000;
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; CHECK-NEXT: ret;
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%z = fadd float %x, 1.0
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ret float %z
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}
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define ptx_device double @t2_f64(double %x) {
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; CHECK: add.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, 0D3FF0000000000000;
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; CHECK-NEXT: ret;
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%z = fadd double %x, 1.0
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ret double %z
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}
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