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https://github.com/c64scene-ar/llvm-6502.git
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6824f127f9
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
2.4 KiB
LLVM
89 lines
2.4 KiB
LLVM
; Test 64-bit atomic exchange.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check register exchange.
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define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK: lg %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: csg %r2, %r4, 0(%r3)
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; CHECK: jl [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw xchg i64 *%src, i64 %b seq_cst
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ret i64 %res
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}
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; Check the high end of the aligned CSG range.
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define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: lg %r2, 524280(%r3)
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; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65535
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%res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
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ret i64 %res
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}
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; Check the next doubleword up, which requires separate address logic.
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define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r3, 524288
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; CHECK: lg %r2, 0(%r3)
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; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65536
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%res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
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ret i64 %res
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}
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; Check the low end of the CSG range.
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define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: lg %r2, -524288(%r3)
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; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65536
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%res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
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ret i64 %res
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}
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; Check the next doubleword down, which requires separate address logic.
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define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
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; CHECK-LABEL: f5:
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; CHECK: agfi %r3, -524296
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; CHECK: lg %r2, 0(%r3)
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; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65537
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%res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
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ret i64 %res
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}
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; Check that indexed addresses are not allowed.
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define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
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; CHECK-LABEL: f6:
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; CHECK: agr %r3, %r4
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; CHECK: lg %r2, 0(%r3)
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; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i64 *
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%res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst
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ret i64 %res
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}
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; Check exchange of a constant. We should force it into a register and
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; use the sequence above.
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define i64 @f7(i64 %dummy, i64 *%ptr) {
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; CHECK-LABEL: f7:
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; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
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; CHECK: lg %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: csg %r2, [[VALUE]], 0(%r3)
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; CHECK: jl [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw xchg i64 *%ptr, i64 3000000000 seq_cst
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ret i64 %res
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}
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