mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-10 17:29:44 +00:00
6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
4.5 KiB
LLVM
218 lines
4.5 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: sitof32
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; CHECK: vcvtdq2ps %zmm
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; CHECK: ret
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define <16 x float> @sitof32(<16 x i32> %a) nounwind {
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%b = sitofp <16 x i32> %a to <16 x float>
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ret <16 x float> %b
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}
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; CHECK-LABEL: fptosi00
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; CHECK: vcvttps2dq %zmm
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; CHECK: ret
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define <16 x i32> @fptosi00(<16 x float> %a) nounwind {
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%b = fptosi <16 x float> %a to <16 x i32>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: fptoui00
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; CHECK: vcvttps2udq
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; CHECK: ret
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define <16 x i32> @fptoui00(<16 x float> %a) nounwind {
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%b = fptoui <16 x float> %a to <16 x i32>
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ret <16 x i32> %b
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}
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; CHECK-LABEL: fptoui01
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; CHECK: vcvttpd2udq
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; CHECK: ret
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define <8 x i32> @fptoui01(<8 x double> %a) nounwind {
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%b = fptoui <8 x double> %a to <8 x i32>
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ret <8 x i32> %b
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}
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; CHECK-LABEL: sitof64
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; CHECK: vcvtdq2pd %ymm
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; CHECK: ret
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define <8 x double> @sitof64(<8 x i32> %a) {
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%b = sitofp <8 x i32> %a to <8 x double>
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ret <8 x double> %b
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}
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; CHECK-LABEL: fptosi01
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; CHECK: vcvttpd2dq %zmm
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; CHECK: ret
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define <8 x i32> @fptosi01(<8 x double> %a) {
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%b = fptosi <8 x double> %a to <8 x i32>
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ret <8 x i32> %b
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}
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; CHECK-LABEL: fptrunc00
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; CHECK: vcvtpd2ps %zmm
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; CHECK-NEXT: vcvtpd2ps %zmm
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; CHECK-NEXT: vinsertf64x4 $1
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; CHECK: ret
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define <16 x float> @fptrunc00(<16 x double> %b) nounwind {
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%a = fptrunc <16 x double> %b to <16 x float>
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ret <16 x float> %a
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}
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; CHECK-LABEL: fpext00
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; CHECK: vcvtps2pd %ymm0, %zmm0
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; CHECK: ret
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define <8 x double> @fpext00(<8 x float> %b) nounwind {
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%a = fpext <8 x float> %b to <8 x double>
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ret <8 x double> %a
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}
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; CHECK-LABEL: funcA
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; CHECK: vcvtsi2sdqz (%
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; CHECK: ret
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define double @funcA(i64* nocapture %e) {
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entry:
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%tmp1 = load i64* %e, align 8
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%conv = sitofp i64 %tmp1 to double
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ret double %conv
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}
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; CHECK-LABEL: funcB
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; CHECK: vcvtsi2sdlz (%
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; CHECK: ret
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define double @funcB(i32* %e) {
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entry:
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%tmp1 = load i32* %e, align 4
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%conv = sitofp i32 %tmp1 to double
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ret double %conv
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}
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; CHECK-LABEL: funcC
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; CHECK: vcvtsi2sslz (%
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; CHECK: ret
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define float @funcC(i32* %e) {
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entry:
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%tmp1 = load i32* %e, align 4
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%conv = sitofp i32 %tmp1 to float
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ret float %conv
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}
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; CHECK-LABEL: i64tof32
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; CHECK: vcvtsi2ssqz (%
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; CHECK: ret
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define float @i64tof32(i64* %e) {
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entry:
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%tmp1 = load i64* %e, align 8
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%conv = sitofp i64 %tmp1 to float
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ret float %conv
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}
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; CHECK-LABEL: fpext
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; CHECK: vcvtss2sdz
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; CHECK: ret
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define void @fpext() {
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entry:
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%f = alloca float, align 4
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%d = alloca double, align 8
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%tmp = load float* %f, align 4
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%conv = fpext float %tmp to double
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store double %conv, double* %d, align 8
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ret void
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}
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; CHECK-LABEL: fpround_scalar
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; CHECK: vmovsdz
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; CHECK: vcvtsd2ssz
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; CHECK: vmovssz
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; CHECK: ret
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define void @fpround_scalar() nounwind uwtable {
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entry:
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%f = alloca float, align 4
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%d = alloca double, align 8
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%tmp = load double* %d, align 8
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%conv = fptrunc double %tmp to float
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store float %conv, float* %f, align 4
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ret void
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}
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; CHECK-LABEL: long_to_double
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; CHECK: vmovqz
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; CHECK: ret
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define double @long_to_double(i64 %x) {
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%res = bitcast i64 %x to double
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ret double %res
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}
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; CHECK-LABEL: double_to_long
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; CHECK: vmovqz
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; CHECK: ret
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define i64 @double_to_long(double %x) {
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%res = bitcast double %x to i64
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ret i64 %res
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}
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; CHECK-LABEL: int_to_float
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; CHECK: vmovdz
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; CHECK: ret
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define float @int_to_float(i32 %x) {
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%res = bitcast i32 %x to float
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ret float %res
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}
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; CHECK-LABEL: float_to_int
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; CHECK: vmovdz
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; CHECK: ret
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define i32 @float_to_int(float %x) {
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%res = bitcast float %x to i32
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ret i32 %res
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}
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; CHECK-LABEL: uitof64
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; CHECK: vcvtudq2pd
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; CHECK: vextracti64x4
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; CHECK: vcvtudq2pd
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; CHECK: ret
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define <16 x double> @uitof64(<16 x i32> %a) nounwind {
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%b = uitofp <16 x i32> %a to <16 x double>
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ret <16 x double> %b
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}
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; CHECK-LABEL: uitof32
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; CHECK: vcvtudq2ps
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; CHECK: ret
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define <16 x float> @uitof32(<16 x i32> %a) nounwind {
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%b = uitofp <16 x i32> %a to <16 x float>
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ret <16 x float> %b
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}
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; CHECK-LABEL: @fptosi02
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; CHECK vcvttss2siz
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; CHECK: ret
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define i32 @fptosi02(float %a) nounwind {
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%b = fptosi float %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: @fptoui02
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; CHECK vcvttss2usiz
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; CHECK: ret
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define i32 @fptoui02(float %a) nounwind {
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%b = fptoui float %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: @uitofp02
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; CHECK vcvtusi2ss
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; CHECK: ret
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define float @uitofp02(i32 %a) nounwind {
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%b = uitofp i32 %a to float
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ret float %b
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}
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; CHECK-LABEL: @uitofp03
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; CHECK vcvtusi2sd
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; CHECK: ret
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define double @uitofp03(i32 %a) nounwind {
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%b = uitofp i32 %a to double
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ret double %b
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}
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