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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
3.9 KiB
C++
89 lines
3.9 KiB
C++
//===-- AMDILDeviceInfo.h - Constants for describing devices --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//==-----------------------------------------------------------------------===//
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#ifndef AMDILDEVICEINFO_H
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#define AMDILDEVICEINFO_H
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#include <string>
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namespace llvm {
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class AMDGPUDevice;
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class AMDGPUSubtarget;
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namespace AMDGPUDeviceInfo {
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/// Each Capabilities can be executed using a hardware instruction,
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/// emulated with a sequence of software instructions, or not
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/// supported at all.
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enum ExecutionMode {
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Unsupported = 0, ///< Unsupported feature on the card(Default value)
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/// This is the execution mode that is set if the feature is emulated in
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/// software.
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Software,
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/// This execution mode is set if the feature exists natively in hardware
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Hardware
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};
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enum Caps {
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HalfOps = 0x1, ///< Half float is supported or not.
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DoubleOps = 0x2, ///< Double is supported or not.
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ByteOps = 0x3, ///< Byte(char) is support or not.
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ShortOps = 0x4, ///< Short is supported or not.
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LongOps = 0x5, ///< Long is supported or not.
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Images = 0x6, ///< Images are supported or not.
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ByteStores = 0x7, ///< ByteStores available(!HD4XXX).
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ConstantMem = 0x8, ///< Constant/CB memory.
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LocalMem = 0x9, ///< Local/LDS memory.
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PrivateMem = 0xA, ///< Scratch/Private/Stack memory.
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RegionMem = 0xB, ///< OCL GDS Memory Extension.
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FMA = 0xC, ///< Use HW FMA or SW FMA.
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ArenaSegment = 0xD, ///< Use for Arena UAV per pointer 12-1023.
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MultiUAV = 0xE, ///< Use for UAV per Pointer 0-7.
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Reserved0 = 0xF, ///< ReservedFlag
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NoAlias = 0x10, ///< Cached loads.
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Signed24BitOps = 0x11, ///< Peephole Optimization.
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/// Debug mode implies that no hardware features or optimizations
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/// are performned and that all memory access go through a single
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/// uav(Arena on HD5XXX/HD6XXX and Raw on HD4XXX).
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Debug = 0x12,
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CachedMem = 0x13, ///< Cached mem is available or not.
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BarrierDetect = 0x14, ///< Detect duplicate barriers.
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Reserved1 = 0x15, ///< Reserved flag
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ByteLDSOps = 0x16, ///< Flag to specify if byte LDS ops are available.
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ArenaVectors = 0x17, ///< Flag to specify if vector loads from arena work.
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TmrReg = 0x18, ///< Flag to specify if Tmr register is supported.
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NoInline = 0x19, ///< Flag to specify that no inlining should occur.
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MacroDB = 0x1A, ///< Flag to specify that backend handles macrodb.
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HW64BitDivMod = 0x1B, ///< Flag for backend to generate 64bit div/mod.
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ArenaUAV = 0x1C, ///< Flag to specify that arena uav is supported.
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PrivateUAV = 0x1D, ///< Flag to specify that private memory uses uav's.
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/// If more capabilities are required, then
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/// this number needs to be increased.
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/// All capabilities must come before this
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/// number.
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MaxNumberCapabilities = 0x20
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};
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/// These have to be in order with the older generations
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/// having the lower number enumerations.
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enum Generation {
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HD4XXX = 0, ///< 7XX based devices.
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HD5XXX, ///< Evergreen based devices.
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HD6XXX, ///< NI/Evergreen+ based devices.
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HD7XXX, ///< Southern Islands based devices.
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HDTEST, ///< Experimental feature testing device.
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HDNUMGEN
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};
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AMDGPUDevice*
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getDeviceFromName(const std::string &name, AMDGPUSubtarget *ptr,
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bool is64bit = false, bool is64on32bit = false);
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} // namespace AMDILDeviceInfo
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} // namespace llvm
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#endif // AMDILDEVICEINFO_H
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