llvm-6502/test/CodeGen/X86/vec_shuffle-40.ll
Adam Nemet 6f4f46cf11 [X86] Generate VPSHUFB for in-place v16i16 shuffles
This used to resort to splitting the 256-bit operation into two 128-bit
shuffles and then recombining the results.

Fixes <rdar://problem/16167303>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204735 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 17:47:06 +00:00

23 lines
953 B
LLVM

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s
define void @shuffle_v16i16(<16 x i16>* %a) {
; CHECK-LABEL: shuffle_v16i16:
; CHECK: vpshufb {{.*}}%ymm
; CHECK-NOT: vpshufb {{.*}}%xmm
entry:
%0 = load <16 x i16>* %a, align 32
%shuffle = shufflevector <16 x i16> %0, <16 x i16> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
store <16 x i16> %shuffle, <16 x i16>* %a, align 32
ret void
}
define void @shuffle_v16i16_lanecrossing(<16 x i16>* %a) {
; CHECK-LABEL: shuffle_v16i16_lanecrossing:
; CHECK-NOT: vpshufb {{.*}}%ymm
entry:
%0 = load <16 x i16>* %a, align 32
%shuffle = shufflevector <16 x i16> %0, <16 x i16> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 13, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
store <16 x i16> %shuffle, <16 x i16>* %a, align 32
ret void
}