llvm-6502/test/CodeGen/X86/x86-64-tls-1.ll
Benjamin Kramer 3d5694dca9 Fix tests not to depend on specific regalloc or instruction order.
They were failing with -mcpu=atom.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192890 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 12:41:05 +00:00

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443 B
LLVM

; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
@tm_nest_level = internal thread_local global i32 0
define i64 @z() nounwind {
; FIXME: The codegen here is primitive at best and could be much better.
; The add and the moves can be folded together.
; CHECK-DAG: movq $tm_nest_level@TPOFF, %rcx
; CHECK-DAG: movq %fs:0, %rax
; CHECK: addl %ecx, %eax
ret i64 and (i64 ptrtoint (i32* @tm_nest_level to i64), i64 100)
}