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2f69e4cf32
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
20 lines
435 B
LLVM
20 lines
435 B
LLVM
; RUN: true
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; DISABLED: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched < %s | FileCheck %s
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; CHECK: r[[T0:[0-9]+]] = #7
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; CHECK: memw(r29 + #0) = r[[T0]]
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; CHECK: r0 = #1
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; CHECK: r1 = #2
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; CHECK: r2 = #3
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; CHECK: r3 = #4
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; CHECK: r4 = #5
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; CHECK: r5 = #6
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define void @foo() nounwind {
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entry:
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call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
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ret void
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}
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declare void @bar(i32, i32, i32, i32, i32, i32, i32)
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