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2f69e4cf32
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
616 B
LLVM
21 lines
616 B
LLVM
; RUN: true
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; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; CHECK: += mpyi
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define void @foo(i32 %acc, i32 %num, i32 %num2) nounwind {
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entry:
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%acc.addr = alloca i32, align 4
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%num.addr = alloca i32, align 4
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%num2.addr = alloca i32, align 4
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store i32 %acc, i32* %acc.addr, align 4
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store i32 %num, i32* %num.addr, align 4
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store i32 %num2, i32* %num2.addr, align 4
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%0 = load i32* %num.addr, align 4
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%1 = load i32* %acc.addr, align 4
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%mul = mul nsw i32 %0, %1
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%2 = load i32* %num2.addr, align 4
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%add = add nsw i32 %mul, %2
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store i32 %add, i32* %num.addr, align 4
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ret void
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}
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