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5a49125fec
Now that the PowerPC backend can track individual CR bits as first-class registers, we should also have a way of allocating them for inline asm statements. Because these registers are only one bit, if an output variable is implicitly cast to a larger integer size, we'll get an any_extend to that larger type (this is part of the existing target-independent logic). As a result, regardless of the size of the output type, only the first bit is meaningful. The constraint identifier "wc" has been chosen for this purpose. Although gcc does not currently support allocating individual CR bits, this identifier choice has been coordinated with the gcc PowerPC team, and will be marked as reserved for this purpose in the gcc constraints.md file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202657 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.8 KiB
LLVM
60 lines
1.8 KiB
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
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%1 = and i8 %0, 1
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%tobool3 = icmp ne i8 %1, 0
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ret i1 %tobool3
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; CHECK-LABEL: @testi1
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], 1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
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entry:
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%0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
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ret i32 %0
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; The ABI sign_extend should combine with the any_extend from the asm result,
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; and the result will be 0 or -1. This highlights the fact that only the first
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; bit is meaningful.
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; CHECK-LABEL: @testi32
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], -1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0
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ret i8 %0
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; CHECK-LABEL: @testi8
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], 1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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attributes #0 = { nounwind }
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