llvm-6502/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
Evan Cheng 5d088fee7c Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 22:57:19 +00:00

24 lines
963 B
LLVM

; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
define fastcc void @optimize_bit_field() nounwind {
bb4:
%a = load i32* null ; <i32> [#uses=1]
%s = load i32* getelementptr (i32* null, i32 1) ; <i32> [#uses=1]
%z = load i32* getelementptr (i32* null, i32 2) ; <i32> [#uses=1]
%r = bitcast i32 0 to i32 ; <i32> [#uses=1]
%q = trunc i32 %z to i8 ; <i8> [#uses=1]
%b = icmp eq i8 0, %q ; <i1> [#uses=1]
br i1 %b, label %bb73, label %bb72
bb72: ; preds = %bb4
%f = tail call fastcc i32 @gen_lowpart(i32 %r, i32 %a) nounwind ; <i32> [#uses=1]
br label %bb73
bb73: ; preds = %bb72, %bb4
%y = phi i32 [ %f, %bb72 ], [ %s, %bb4 ] ; <i32> [#uses=1]
store i32 %y, i32* getelementptr (i32* null, i32 3)
unreachable
}
declare fastcc i32 @gen_lowpart(i32, i32) nounwind