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Tom Stellard f518f53f5e Merging r228303: 
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r228303 | thomas.stellard | 2015-02-05 10:32:18 -0500 (Thu, 05 Feb 2015) | 11 lines

R600/SI: Fix bug in TTI loop unrolling preferences

We should be setting UnrollingPreferences::MaxCount to MAX_UINT instead
of UnrollingPreferences::Count.

Count is a 'forced unrolling factor', while MaxCount sets an upper
limit to the unrolling factor.

Setting Count to MAX_UINT was causing the loop in the testcase to be
unrolled 15 times, when it only had a maximum of 4 iterations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@228320 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 18:05:18 +00:00
..
AsmParser
R600/SI: Add a stub GCNTargetMachine
2015-01-06 18:00:21 +00:00
InstPrinter
[cleanup] Re-sort all the #include lines in LLVM using
2015-01-14 11:23:27 +00:00
MCTargetDesc
Port r226022 to the 3.6 branch.
2015-01-17 00:38:54 +00:00
TargetInfo
R600/SI: Add a stub GCNTargetMachine
2015-01-06 18:00:21 +00:00
AMDGPU.h
Merging r226586:
2015-01-21 22:44:48 +00:00
AMDGPU.td
Merging r226597:
2015-01-21 22:44:52 +00:00
AMDGPUAlwaysInlinePass.cpp
Reapply: R600: Make sure to inline all internal functions
2014-11-03 19:49:05 +00:00
AMDGPUAsmPrinter.cpp
Merging r226970:
2015-01-28 20:46:16 +00:00
AMDGPUAsmPrinter.h
R600/SI: Emit amd_kernel_code_t header for AMDGPU environment
2014-12-02 22:00:07 +00:00
AMDGPUCallingConv.td
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUInstrInfo.cpp
Merging r226188:
2015-01-21 22:44:37 +00:00
AMDGPUInstrInfo.h
Merging r226188:
2015-01-21 22:44:37 +00:00
AMDGPUInstrInfo.td
R600/SI: Add class intrinsic
2015-01-06 23:00:37 +00:00
AMDGPUInstructions.td
R600/SI: Make more unordered comparisons legal
2014-12-11 22:15:39 +00:00
AMDGPUIntrinsicInfo.cpp
…
AMDGPUIntrinsicInfo.h
…
AMDGPUIntrinsics.td
…
AMDGPUISelDAGToDAG.cpp
Merging r226945:
2015-01-28 20:46:14 +00:00
AMDGPUISelLowering.cpp
Merging r226945:
2015-01-28 20:46:14 +00:00
AMDGPUISelLowering.h
R600: Implement getRecipEstimate
2015-01-13 20:53:23 +00:00
AMDGPUMachineFunction.cpp
…
AMDGPUMachineFunction.h
…
AMDGPUMCInstLower.cpp
Merging r226586:
2015-01-21 22:44:48 +00:00
AMDGPUMCInstLower.h
Merging r226188:
2015-01-21 22:44:37 +00:00
AMDGPUPromoteAlloca.cpp
R600: Don't promote allocas when one of the users is a ptrtoint instruction
2014-10-31 20:52:04 +00:00
AMDGPURegisterInfo.cpp
R600/SI: Enable inline assembly
2014-12-03 04:08:00 +00:00
AMDGPURegisterInfo.h
…
AMDGPURegisterInfo.td
…
AMDGPUSubtarget.cpp
R600/SI: Define a schedule model and enable the generic machine scheduler
2015-01-30 18:55:30 +00:00
AMDGPUSubtarget.h
R600/SI: Define a schedule model and enable the generic machine scheduler
2015-01-30 18:55:30 +00:00
AMDGPUTargetMachine.cpp
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
AMDGPUTargetMachine.h
R600/SI: Add a stub GCNTargetMachine
2015-01-06 18:00:21 +00:00
AMDGPUTargetTransformInfo.cpp
Merging r228303:
2015-02-05 18:05:18 +00:00
AMDILCFGStructurizer.cpp
…
AMDKernelCodeT.h
R600/SI: Emit amd_kernel_code_t header for AMDGPU environment
2014-12-02 22:00:07 +00:00
CaymanInstructions.td
…
CIInstructions.td
R600/SI: Add VI instructions
2014-12-07 12:18:57 +00:00
CMakeLists.txt
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
EvergreenInstructions.td
R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs
2014-11-02 23:46:54 +00:00
LLVMBuild.txt
R600/SI: Start implementing an assembler
2014-11-14 14:08:00 +00:00
Makefile
R600/SI: Start implementing an assembler
2014-11-14 14:08:00 +00:00
Processors.td
R600/SI: Define a schedule model
2015-01-14 01:13:19 +00:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
…
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
…
R600InstrFormats.td
R600/SI: Start implementing an assembler
2014-11-14 14:08:00 +00:00
R600InstrInfo.cpp
…
R600InstrInfo.h
…
R600Instructions.td
R600/SI: Use unordered not equal instructions
2014-12-11 22:15:35 +00:00
R600Intrinsics.td
…
R600ISelLowering.cpp
[SelectionDAG] Allow targets to specify legality of extloads' result
2015-01-08 00:51:32 +00:00
R600ISelLowering.h
…
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
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R600MachineScheduler.h
…
R600OptimizeVectorRegisters.cpp
…
R600Packetizer.cpp
…
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600TextureIntrinsicsReplacer.cpp
…
R700Instructions.td
…
SIAnnotateControlFlow.cpp
Merging r228302:
2015-02-05 18:05:15 +00:00
SIDefines.h
Merging r226597:
2015-01-21 22:44:52 +00:00
SIFixSGPRCopies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp
…
SIFoldOperands.cpp
R600/SI: Add pattern for bitcasting fp immediates to integers
2015-01-13 22:59:41 +00:00
SIInsertWaits.cpp
R600/SI: Insert s_waitcnt before s_barrier instructions.
2015-01-06 19:52:07 +00:00
SIInstrFormats.td
Merging r226187:
2015-01-21 22:44:35 +00:00
SIInstrInfo.cpp
Merging r226597:
2015-01-21 22:44:52 +00:00
SIInstrInfo.h
Merging r226188:
2015-01-21 22:44:37 +00:00
SIInstrInfo.td
Merging r226226:
2015-01-21 22:44:43 +00:00
SIInstructions.td
Merging r226586:
2015-01-21 22:44:48 +00:00
SIIntrinsics.td
…
SIISelLowering.cpp
Merging r226597:
2015-01-21 22:44:52 +00:00
SIISelLowering.h
R600/SI: Fix bad code with unaligned byte vector loads
2015-01-14 01:35:22 +00:00
SILoadStoreOptimizer.cpp
R600/SI: Fix live range error hidden by SIFoldOperands
2014-12-03 05:22:29 +00:00
SILowerControlFlow.cpp
R600/SI: Add pattern for bitcasting fp immediates to integers
2015-01-13 22:59:41 +00:00
SILowerI1Copies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
SIMachineFunctionInfo.h
Merging r226597:
2015-01-21 22:44:52 +00:00
SIPrepareScratchRegs.cpp
Merging r226596:
2015-01-21 22:44:51 +00:00
SIRegisterInfo.cpp
Merging r227618:
2015-02-02 18:10:46 +00:00
SIRegisterInfo.h
R600/SI: Define a schedule model and enable the generic machine scheduler
2015-01-30 18:55:30 +00:00
SIRegisterInfo.td
R600/SI: Use RegisterOperands to specify which operands can accept immediates
2015-01-12 19:33:18 +00:00
SISchedule.td
R600/SI: Define a schedule model
2015-01-14 01:13:19 +00:00
SIShrinkInstructions.cpp
Merging r226188:
2015-01-21 22:44:37 +00:00
SITypeRewriter.cpp
Revert "IR: MDNode => Value"
2014-11-11 21:30:22 +00:00
VIInstrFormats.td
R600/SI: Add VI instructions
2014-12-07 12:18:57 +00:00
VIInstructions.td
Merging r226191:
2015-01-21 22:44:42 +00:00