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https://github.com/c64scene-ar/llvm-6502.git
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7d9f2b93a3
long test(long x) { return (x & 123124) | 3; }
Currently compiles to:
_test:
orl $3, %edi
movq %rdi, %rax
andq $123127, %rax
ret
This is because instruction and DAG combiners canonicalize
(or (and x, C), D) -> (and (or, D), (C | D))
However, this is only profitable if (C & D) != 0. It gets in the way of the
3-addressification because the input bits are known to be zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97616 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.1 KiB
LLVM
54 lines
1.1 KiB
LLVM
; This test makes sure that these instructions are properly eliminated.
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;
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; PR1253
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define i1 @test0(i32 %A) {
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; CHECK: @test0
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; CHECK: %C = icmp slt i32 %A, 0
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%B = xor i32 %A, -2147483648
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%C = icmp sgt i32 %B, -1
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ret i1 %C
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}
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define i1 @test1(i32 %A) {
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; CHECK: @test1
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; CHECK: %C = icmp slt i32 %A, 0
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%B = xor i32 %A, 12345
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%C = icmp slt i32 %B, 0
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ret i1 %C
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}
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; PR1014
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define i32 @test2(i32 %tmp1) {
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; CHECK: @test2
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; CHECK-NEXT: and i32 %tmp1, 32
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; CHECK-NEXT: or i32 %ovm, 8
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; CHECK-NEXT: ret i32
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%ovm = and i32 %tmp1, 32
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%ov3 = add i32 %ovm, 145
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%ov110 = xor i32 %ov3, 153
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ret i32 %ov110
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}
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define i32 @test3(i32 %tmp1) {
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; CHECK: @test3
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; CHECK-NEXT: and i32 %tmp1, 32
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; CHECK-NEXT: or i32 %tmp, 8
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; CHECK-NEXT: ret i32
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%ovm = or i32 %tmp1, 145
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%ov31 = and i32 %ovm, 177
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%ov110 = xor i32 %ov31, 153
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ret i32 %ov110
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}
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define i32 @test4(i32 %A, i32 %B) {
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%1 = xor i32 %A, -1
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%2 = ashr i32 %1, %B
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%3 = xor i32 %2, -1
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ret i32 %3
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; CHECK: @test4
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; CHECK: %1 = ashr i32 %A, %B
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; CHECK: ret i32 %1
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}
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