Chandler Carruth 2ff4a49344 [x86] Fix a bad predicate I spotted by inspection -- pshufhw and pshuflw ... were added in SSE2, no SSSE3. Found this while auditing all uses of SSSE3 in the X86 target. I don't actually expect this to make a significant difference on anything and I don't have any detailed test cases but I updated the existing test cases that already covered some of this code path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209056 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-17 03:29:20 +00:00
..
AArch64	Revert "Implement global merge optimization for global variables."	2014-05-16 13:02:18 +00:00
ARM	Fix most of PR10367.	2014-05-16 19:35:39 +00:00
ARM64	[ARM64] Increases the Sched Model accuracy for Cortex-A53.	2014-05-16 17:15:33 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
Inputs
Mips	Finish materialize for ints	2014-05-15 21:54:15 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
R600	R600/SI: Promote f32 SELECT to i32	2014-05-16 20:56:41 +00:00
SPARC	TableGen: fix operand counting for aliases	2014-05-16 09:42:04 +00:00
SystemZ	Reenable use of TBAA during CodeGen	2014-04-12 01:26:00 +00:00
Thumb	Re-enable inline memcpy expansion for Thumb1.	2014-05-16 14:24:22 +00:00
Thumb2	Fix the Load/Store optimization pass to work with Thumb1.	2014-05-16 14:14:30 +00:00
X86	[x86] Fix a bad predicate I spotted by inspection -- pshufhw and pshuflw	2014-05-17 03:29:20 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00