Owen Anderson 3042a65e5f Remove a very old instcombine where we would turn sequences of selects into ... logical operations on the i1's driving them. This is a bad idea for every target I can think of (confirmed with micro tests on all of: x86-64, ARM, AArch64, Mips, and PowerPC) because it forces the i1 to be materialized into a general purpose register, whereas consuming it directly into a select generally allows it to exist only transiently in a predicate or flags register. Chandler ran a set of performance tests with this change, and reported no measurable change on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201275 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-12 23:54:07 +00:00
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Analysis	[Vectorizer] Add a new 'OperandValueKind' in TargetTransformInfo called	2014-02-12 23:43:47 +00:00
Assembler
Bindings
Bitcode
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CodeGen	[X86] Teach the backend how to lower vector shift left into multiply rather than scalarizing it.	2014-02-12 23:42:28 +00:00
DebugInfo	DebugInfo: Demonstrate that we're not currently uniquing address table entries in fission	2014-02-12 23:03:54 +00:00
ExecutionEngine	PC-rel implemented in AArch64, test now pass	2014-02-12 17:17:41 +00:00
Feature
FileCheck
Instrumentation	[asan] support for FreeBSD, LLVM part. patch by Viktor Kutuzov	2014-02-10 07:37:04 +00:00
Integer
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MC	Tidy up a bit. Formatting only.	2014-02-11 20:48:41 +00:00
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Transforms	Remove a very old instcombine where we would turn sequences of selects into	2014-02-12 23:54:07 +00:00
Unit
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.clang-format
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