mirror of
https://github.com/c64scene-ar/llvm-6502.git
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304d0f3076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19764 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
3.4 KiB
TableGen
94 lines
3.4 KiB
TableGen
//===- AlphaRegisterInfo.td - The Alpha Register File --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class AlphaReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "Alpha";
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}
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// We identify all our registers with a 5-bit ID, for consistency's sake.
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// GPR - One of the 32 32-bit general-purpose registers
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class GPR<bits<5> num, string n> : AlphaReg<n> {
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let Num = num;
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}
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// FPR - One of the 32 64-bit floating-point registers
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class FPR<bits<5> num, string n> : AlphaReg<n> {
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let Num = num;
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}
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//#define FP $15
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//#define RA $26
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//#define PV $27
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//#define GP $29
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//#define SP $30
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// General-purpose registers
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def R0 : GPR< 0, "$0">; def R1 : GPR< 1, "$1">;
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def R2 : GPR< 2, "$2">; def R3 : GPR< 3, "$3">;
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def R4 : GPR< 4, "$4">; def R5 : GPR< 5, "$5">;
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def R6 : GPR< 6, "$6">; def R7 : GPR< 7, "$7">;
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def R8 : GPR< 8, "$8">; def R9 : GPR< 9, "$9">;
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def R10 : GPR<10, "$10">; def R11 : GPR<11, "$11">;
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def R12 : GPR<12, "$12">; def R13 : GPR<13, "$13">;
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def R14 : GPR<14, "$14">; def R15 : GPR<15, "$15">;
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def R16 : GPR<16, "$16">; def R17 : GPR<17, "$17">;
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def R18 : GPR<18, "$18">; def R19 : GPR<19, "$19">;
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def R20 : GPR<20, "$20">; def R21 : GPR<21, "$21">;
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def R22 : GPR<22, "$22">; def R23 : GPR<23, "$23">;
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def R24 : GPR<24, "$24">; def R25 : GPR<25, "$25">;
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def R26 : GPR<26, "$26">; def R27 : GPR<27, "$27">;
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def R28 : GPR<28, "$28">; def R29 : GPR<29, "$29">;
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def R30 : GPR<30, "$30">; def R31 : GPR<31, "$31">;
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// Floating-point registers
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def F0 : FPR< 0, "F0">; def F1 : FPR< 1, "F1">;
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def F2 : FPR< 2, "F2">; def F3 : FPR< 3, "F3">;
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def F4 : FPR< 4, "F4">; def F5 : FPR< 5, "F5">;
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def F6 : FPR< 6, "F6">; def F7 : FPR< 7, "F7">;
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def F8 : FPR< 8, "F8">; def F9 : FPR< 9, "F9">;
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def F10 : FPR<10, "F10">; def F11 : FPR<11, "F11">;
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def F12 : FPR<12, "F12">; def F13 : FPR<13, "F13">;
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def F14 : FPR<14, "F14">; def F15 : FPR<15, "F15">;
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def F16 : FPR<16, "F16">; def F17 : FPR<17, "F17">;
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def F18 : FPR<18, "F18">; def F19 : FPR<19, "F19">;
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def F20 : FPR<20, "F20">; def F21 : FPR<21, "F21">;
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def F22 : FPR<22, "F22">; def F23 : FPR<23, "F23">;
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def F24 : FPR<24, "F24">; def F25 : FPR<25, "F25">;
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def F26 : FPR<26, "F26">; def F27 : FPR<27, "F27">;
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def F28 : FPR<28, "F28">; def F29 : FPR<29, "F29">;
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def F30 : FPR<30, "F30">; def F31 : FPR<31, "F31">;
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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// //#define GP $29
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// //#define SP $30
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// $28 is undefined after any and all calls
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/// Register classes
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def GPRC : RegisterClass<i64, 64,
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//Volitle
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[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27,
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//Non-Volitile
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R9, R10, R11, R12, R13, R14, R15, R26, /*R28,*/ R29, R30, R31]>;
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//R28 is reserved for the assembler
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//Don't allocate 15, 29, 30, 31
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//Allocation volatiles only for now
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def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9,
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F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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