mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b118a073d7
- Rewrite/merge pseudo-atomic instruction emitters to address the
following issue:
* Reduce one unnecessary load in spin-loop
previously the spin-loop looks like
thisMBB:
newMBB:
ld t1 = [bitinstr.addr]
op t2 = t1, [bitinstr.val]
not t3 = t2 (if Invert)
mov EAX = t1
lcs dest = [bitinstr.addr], t3 [EAX is implicit]
bz newMBB
fallthrough -->nextMBB
the 'ld' at the beginning of newMBB should be lift out of the loop
as lcs (or CMPXCHG on x86) will load the current memory value into
EAX. This loop is refined as:
thisMBB:
EAX = LOAD [MI.addr]
mainMBB:
t1 = OP [MI.val], EAX
LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
JNE mainMBB
sinkMBB:
* Remove immopc as, so far, all pseudo-atomic instructions has
all-register form only, there is no immedidate operand.
* Remove unnecessary attributes/modifiers in pseudo-atomic instruction
td
* Fix issues in PR13458
- Add comprehensive tests on atomic ops on various data types.
NOTE: Some of them are turned off due to missing functionality.
- Revise tests due to the new spin-loop generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
420 lines
19 KiB
C++
420 lines
19 KiB
C++
//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRUCTIONINFO_H
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#define X86INSTRUCTIONINFO_H
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#include "X86.h"
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#include "X86RegisterInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "X86GenInstrInfo.inc"
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namespace llvm {
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class X86RegisterInfo;
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class X86TargetMachine;
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namespace X86 {
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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// Artificial condition codes. These are used by AnalyzeBranch
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// to indicate a block terminated with two conditional branches to
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// the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
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// which can't be represented on x86 with a single condition. These
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// are never used in MachineInstrs.
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COND_NE_OR_P,
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COND_NP_OR_E,
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COND_INVALID
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};
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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// Turn CMov opcode into condition code.
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CondCode getCondFromCMovOpc(unsigned Opc);
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(X86::CondCode CC);
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} // end namespace X86;
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/// isGlobalStubReference - Return true if the specified TargetFlag operand is
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/// a reference to a stub for a global, not the global itself.
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inline static bool isGlobalStubReference(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_DLLIMPORT: // dllimport stub.
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case X86II::MO_GOTPCREL: // rip-relative GOT reference.
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case X86II::MO_GOT: // normal GOT reference.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
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return true;
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default:
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return false;
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}
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}
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/// isGlobalRelativeToPICBase - Return true if the specified global value
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/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
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/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
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inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
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case X86II::MO_GOT: // isPICStyleGOT: other global.
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case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
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case X86II::MO_TLVP: // ??? Pretty sure..
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return true;
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default:
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return false;
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}
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}
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inline static bool isScale(const MachineOperand &MO) {
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return MO.isImm() &&
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(MO.getImm() == 1 || MO.getImm() == 2 ||
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MO.getImm() == 4 || MO.getImm() == 8);
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}
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inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFI()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isReg() &&
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(MI->getOperand(Op+3).isImm() ||
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MI->getOperand(Op+3).isGlobal() ||
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MI->getOperand(Op+3).isCPI() ||
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MI->getOperand(Op+3).isJTI());
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}
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inline static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFI()) return true;
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return Op+5 <= MI->getNumOperands() &&
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MI->getOperand(Op+4).isReg() &&
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isLeaMem(MI, Op);
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}
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class X86InstrInfo : public X86GenInstrInfo {
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X86TargetMachine &TM;
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const X86RegisterInfo RI;
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/// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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/// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
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///
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typedef DenseMap<unsigned,
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std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
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RegOp2MemOpTableType RegOp2MemOpTable2Addr;
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RegOp2MemOpTableType RegOp2MemOpTable0;
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RegOp2MemOpTableType RegOp2MemOpTable1;
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RegOp2MemOpTableType RegOp2MemOpTable2;
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RegOp2MemOpTableType RegOp2MemOpTable3;
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/// MemOp2RegOpTable - Load / store unfolding opcode map.
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///
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typedef DenseMap<unsigned,
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std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
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MemOp2RegOpTableType MemOp2RegOpTable;
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static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
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MemOp2RegOpTableType &M2RTable,
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unsigned RegOp, unsigned MemOp, unsigned Flags);
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public:
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explicit X86InstrInfo(X86TargetMachine &tm);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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/// SubIdx.
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virtual bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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// Branch analysis.
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virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual bool canInsertSelect(const MachineBasicBlock&,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned, unsigned, int&, int&, int&) const;
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virtual void insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned TrueReg, unsigned FalseReg) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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virtual
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MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
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int FrameIx, uint64_t Offset,
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const MDNode *MDPtr,
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DebugLoc DL) const;
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/// foldMemoryOperand - If this target supports it, fold a load or store of
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/// the specified stack slot into the specified machine instruction for the
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/// specified operand(s). If this is possible, the target should perform the
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/// folding and return true, otherwise it should return false. If it folds
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/// the instruction, it is likely that the MachineInstruction the iterator
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/// references has been changed.
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const;
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/// canFoldMemoryOperand - Returns true if the specified load / store is
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/// folding is possible.
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virtual bool canFoldMemoryOperand(const MachineInstr*,
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const SmallVectorImpl<unsigned> &) const;
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/// unfoldMemoryOperand - Separate a single instruction which folded a load or
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/// a store or a load and a store into two or more instruction. If this is
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/// possible, returns true as well as the new instructions by reference.
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virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode*> &NewNodes) const;
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/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
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/// instruction after load / store are unfolded from an instruction of the
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/// specified opcode. It returns zero if the specified unfolding is not
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/// possible. If LoadRegIndex is non-null, it is filled in with the operand
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/// index of the operand which will hold the register holding the loaded
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/// value.
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virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore,
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unsigned *LoadRegIndex = 0) const;
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/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
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/// to determine if two loads are loading from the same base address. It
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/// should only return true if the base pointers are the same and the
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/// only differences between the two addresses are the offset. It also returns
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/// the offsets by reference.
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virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1, int64_t &Offset2) const;
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/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
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/// be scheduled togther. On some targets if two loads are loading from
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/// addresses in the same cache line, it's better if they are scheduled
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/// together. This function takes two integers that represent the load offsets
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/// from the common base address. It returns true if it decides it's desirable
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/// to schedule the two loads together. "NumLoads" is the number of loads that
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/// have already been scheduled after Load1.
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virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const;
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virtual void getNoopForMachoTarget(MCInst &NopInst) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
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/// instruction that defines the specified register class.
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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static bool isX86_64ExtendedReg(const MachineOperand &MO) {
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if (!MO.isReg()) return false;
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return X86II::isX86_64ExtendedReg(MO.getReg());
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}
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned getGlobalBaseReg(MachineFunction *MF) const;
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std::pair<uint16_t, uint16_t>
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getExecutionDomain(const MachineInstr *MI) const;
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void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
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unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
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const TargetRegisterInfo *TRI) const;
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void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
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const TargetRegisterInfo *TRI) const;
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MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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unsigned OpNum,
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const SmallVectorImpl<MachineOperand> &MOs,
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unsigned Size, unsigned Alignment) const;
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bool isHighLatencyDef(int opc) const;
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bool hasHighOperandLatency(const InstrItineraryData *ItinData,
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const MachineRegisterInfo *MRI,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2 if having two register operands, and the value it
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/// compares against in CmpValue. Return true if the comparison instruction
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/// can be analyzed.
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virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2,
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int &CmpMask, int &CmpValue) const;
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/// optimizeCompareInstr - Check if there exists an earlier instruction that
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/// operates on the same source operands and sets flags in the same way as
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/// Compare; remove Compare if possible.
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virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const;
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/// optimizeLoadInstr - Try to remove the load by folding it to a register
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/// operand at the use. We fold the load instructions if and only if the
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/// def and use are in the same BB. We only look at one load and see
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/// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
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/// defined by the load we are trying to fold. DefMI returns the machine
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/// instruction that defines FoldAsLoadDefReg, and the function returns
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/// the machine instruction generated due to folding.
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virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
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const MachineRegisterInfo *MRI,
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unsigned &FoldAsLoadDefReg,
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MachineInstr *&DefMI) const;
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private:
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MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
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MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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/// isFrameOperand - Return true and the FrameIndex if the specified
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/// operand and follow operands form a reference to the stack frame.
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bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
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int &FrameIndex) const;
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};
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} // End llvm namespace
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#endif
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