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73282018a1
Right now the load may not get DCE'd because of the side-effect of updating the base pointer. This can happen if we lower a read-modify-write of an illegal larger type (e.g. i48) such that the modification only affects one of the subparts (the lower i32 part but not the higher i16 part). See the testcase. In order to spot the dead load we need to revisit it when SimplifyDemandedBits decided that the value of the load is masked off. This is the CommitTargetLoweringOpt piece. I checked compile time with ARM64 by sending SPEC bitcode files through llc. No measurable change. Fixes <rdar://problem/16031651> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208640 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
847 B
LLVM
30 lines
847 B
LLVM
; RUN: llc -mcpu=cyclone < %s | FileCheck %s
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target datalayout = "e-i64:64-n32:64-S128"
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target triple = "arm64-apple-ios"
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%"struct.SU" = type { i32, %"struct.SU"*, i32*, i32, i32, %"struct.BO", i32, [5 x i8] }
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%"struct.BO" = type { %"struct.RE" }
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%"struct.RE" = type { i32, i32, i32, i32 }
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; This is a read-modify-write of some bifields combined into an i48. It gets
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; legalized into i32 and i16 accesses. Only a single store of zero to the low
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; i32 part should be live.
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; CHECK-LABEL: test:
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; CHECK-NOT: ldr
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; CHECK: str wzr
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; CHECK-NOT: str
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define void @test(%"struct.SU"* nocapture %su) {
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entry:
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%r1 = getelementptr inbounds %"struct.SU"* %su, i64 1, i32 5
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%r2 = bitcast %"struct.BO"* %r1 to i48*
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%r3 = load i48* %r2, align 8
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%r4 = and i48 %r3, -4294967296
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%r5 = or i48 0, %r4
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store i48 %r5, i48* %r2, align 8
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ret void
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}
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