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291cd09645
We need to use a temporary register for a 2-step operation like REM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.1 KiB
LLVM
45 lines
1.1 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
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; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
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; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
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; REQUIRES: asserts
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; CHECK-SSA-LABEL: Machine code for function t1
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; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
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; CHECK-SSA-NOT: [[QUOTREG]]<def> =
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; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
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; CHECK-SSA-LABEL: Machine code for function t2
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define i32 @t1(i32 %a, i32 %b) {
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; CHECK: @t1
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; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
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; CHECK: msub w0, [[TMP]], w1, w0
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%1 = srem i32 %a, %b
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ret i32 %1
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}
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define i64 @t2(i64 %a, i64 %b) {
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; CHECK: @t2
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; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
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; CHECK: msub x0, [[TMP]], x1, x0
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%1 = srem i64 %a, %b
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ret i64 %1
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}
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define i32 @t3(i32 %a, i32 %b) {
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; CHECK: @t3
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; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
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; CHECK: msub w0, [[TMP]], w1, w0
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%1 = urem i32 %a, %b
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ret i32 %1
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}
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define i64 @t4(i64 %a, i64 %b) {
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; CHECK: @t4
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; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
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; CHECK: msub x0, [[TMP]], x1, x0
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%1 = urem i64 %a, %b
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ret i64 %1
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}
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