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6d35326cd5
Needs to be bottom up because constant values may be forward-substituted to their uses (i.e., into the parent in the BURG tree). 2. Move most of the constant-fixup code into machine-indepedent file InstrSelectionSupport.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@859 91177308-0d34-0410-b5e6-96231b3b80d8
405 lines
13 KiB
C++
405 lines
13 KiB
C++
// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// InstrSelectionSupport.h
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//
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// Purpose:
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// Target-independent instruction selection code.
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// See SparcInstrSelection.cpp for usage.
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//
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// History:
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// 10/10/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/ConstPoolVals.h"
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#include "llvm/Instruction.h"
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#include "llvm/Type.h"
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#include "llvm/iMemory.h"
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//*************************** Local Functions ******************************/
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static TmpInstruction*
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InsertCodeToLoadConstant(Value* opValue,
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Instruction* vmInstr,
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vector<MachineInstr*>& loadConstVec,
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TargetMachine& target)
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{
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vector<TmpInstruction*> tempVec;
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// Create a tmp virtual register to hold the constant.
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TmpInstruction* tmpReg =
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new TmpInstruction(TMP_INSTRUCTION_OPCODE, opValue, NULL);
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vmInstr->getMachineInstrVec().addTempValue(tmpReg);
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target.getInstrInfo().CreateCodeToLoadConst(opValue, tmpReg,
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loadConstVec, tempVec);
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// Register the new tmp values created for this m/c instruction sequence
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for (unsigned i=0; i < tempVec.size(); i++)
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vmInstr->getMachineInstrVec().addTempValue(tempVec[i]);
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// Record the mapping from the tmp VM instruction to machine instruction.
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// Do this for all machine instructions that were not mapped to any
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// other temp values created by
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// tmpReg->addMachineInstruction(loadConstVec.back());
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return tmpReg;
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}
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//---------------------------------------------------------------------------
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// Function GetConstantValueAsSignedInt
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//
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// Convenience function to get the value of an integer constant, for an
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// appropriate integer or non-integer type that can be held in an integer.
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// The type of the argument must be the following:
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// Signed or unsigned integer
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// Boolean
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// Pointer
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//
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// isValidConstant is set to true if a valid constant was found.
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//---------------------------------------------------------------------------
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int64_t
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GetConstantValueAsSignedInt(const Value *V,
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bool &isValidConstant)
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{
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if (!isa<ConstPoolVal>(V))
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{
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isValidConstant = false;
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return 0;
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}
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isValidConstant = true;
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if (V->getType() == Type::BoolTy)
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return (int64_t) ((ConstPoolBool*)V)->getValue();
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if (V->getType()->isIntegral())
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{
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if (V->getType()->isSigned())
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return ((ConstPoolSInt*)V)->getValue();
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assert(V->getType()->isUnsigned());
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uint64_t Val = ((ConstPoolUInt*)V)->getValue();
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if (Val < INT64_MAX) // then safe to cast to signed
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return (int64_t)Val;
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}
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isValidConstant = false;
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return 0;
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}
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//---------------------------------------------------------------------------
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// Function: FoldGetElemChain
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//
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// Purpose:
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// Fold a chain of GetElementPtr instructions into an equivalent
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// (Pointer, IndexVector) pair. Returns the pointer Value, and
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// stores the resulting IndexVector in argument chainIdxVec.
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//---------------------------------------------------------------------------
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Value*
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FoldGetElemChain(const InstructionNode* getElemInstrNode,
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vector<ConstPoolVal*>& chainIdxVec)
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{
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MemAccessInst* getElemInst = (MemAccessInst*)
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getElemInstrNode->getInstruction();
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// Initialize return values from the incoming instruction
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Value* ptrVal = getElemInst->getPtrOperand();
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chainIdxVec = getElemInst->getIndexVec(); // copies index vector values
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// Now chase the chain of getElementInstr instructions, if any
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InstrTreeNode* ptrChild = getElemInstrNode->leftChild();
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while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
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ptrChild->getOpLabel() == GetElemPtrIdx)
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{
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// Child is a GetElemPtr instruction
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getElemInst = (MemAccessInst*)
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((InstructionNode*) ptrChild)->getInstruction();
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const vector<ConstPoolVal*>& idxVec = getElemInst->getIndexVec();
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// Get the pointer value out of ptrChild and *prepend* its index vector
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ptrVal = getElemInst->getPtrOperand();
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chainIdxVec.insert(chainIdxVec.begin(), idxVec.begin(), idxVec.end());
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ptrChild = ptrChild->leftChild();
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}
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return ptrVal;
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}
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//------------------------------------------------------------------------
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// Function Set2OperandsFromInstr
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// Function Set3OperandsFromInstr
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//
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// For the common case of 2- and 3-operand arithmetic/logical instructions,
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// set the m/c instr. operands directly from the VM instruction's operands.
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// Check whether the first or second operand is 0 and can use a dedicated "0"
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// register.
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// Check whether the second operand should use an immediate field or register.
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// (First and third operands are never immediates for such instructions.)
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//
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// Arguments:
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// canDiscardResult: Specifies that the result operand can be discarded
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// by using the dedicated "0"
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//
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// op1position, op2position and resultPosition: Specify in which position
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// in the machine instruction the 3 operands (arg1, arg2
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// and result) should go.
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//
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// RETURN VALUE: unsigned int flags, where
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// flags & 0x01 => operand 1 is constant and needs a register
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// flags & 0x02 => operand 2 is constant and needs a register
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//------------------------------------------------------------------------
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void
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Set2OperandsFromInstr(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int resultPosition)
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{
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Set3OperandsFromInstr(minstr, vmInstrNode, target,
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canDiscardResult, op1Position,
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/*op2Position*/ -1, resultPosition);
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}
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void
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Set3OperandsFromInstr(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int op2Position,
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int resultPosition)
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{
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assert(op1Position >= 0);
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assert(resultPosition >= 0);
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// operand 1
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minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
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vmInstrNode->leftChild()->getValue());
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// operand 2 (if any)
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if (op2Position >= 0)
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minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
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vmInstrNode->rightChild()->getValue());
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// result operand: if it can be discarded, use a dead register if one exists
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if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
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minstr->SetMachineOperand(resultPosition,
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target.getRegInfo().getZeroRegNum());
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else
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minstr->SetMachineOperand(resultPosition,
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MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(Value* val,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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// Check for the common case first: argument is not constant
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//
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ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(val);
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if (!CPV) return opType;
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if (CPV->getType() == Type::BoolTy)
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{
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ConstPoolBool *CPB = (ConstPoolBool*)CPV;
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if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
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{
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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return MachineOperand::MO_MachineRegister;
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}
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getImmedValue = 1;
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return MachineOperand::MO_SignExtendedImmed;
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}
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if (!CPV->getType()->isIntegral()) return opType;
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// Now get the constant value and check if it fits in the IMMED field.
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// Take advantage of the fact that the max unsigned value will rarely
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// fit into any IMMED field and ignore that case (i.e., cast smaller
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// unsigned constants to signed).
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//
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int64_t intValue;
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if (CPV->getType()->isSigned())
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{
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intValue = ((ConstPoolSInt*)CPV)->getValue();
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}
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else
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{
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uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
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if (V >= INT64_MAX) return opType;
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intValue = (int64_t)V;
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}
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if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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}
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else if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
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{
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opType = MachineOperand::MO_SignExtendedImmed;
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getImmedValue = intValue;
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}
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return opType;
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}
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//---------------------------------------------------------------------------
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// Function: FixConstantOperandsForInstr
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//
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// Purpose:
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// Special handling for constant operands of a machine instruction
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// -- if the constant is 0, use the hardwired 0 register, if any;
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// -- if the constant fits in the IMMEDIATE field, use that field;
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// -- else create instructions to put the constant into a register, either
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// directly or by loading explicitly from the constant pool.
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//
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// In the first 2 cases, the operand of `minstr' is modified in place.
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// Returns a vector of machine instructions generated for operands that
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// fall under case 3; these must be inserted before `minstr'.
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//---------------------------------------------------------------------------
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vector<MachineInstr*>
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FixConstantOperandsForInstr(Instruction* vmInstr,
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MachineInstr* minstr,
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TargetMachine& target)
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{
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vector<MachineInstr*> loadConstVec;
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const MachineInstrDescriptor& instrDesc =
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target.getInstrInfo().getDescriptor(minstr->getOpCode());
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for (unsigned op=0; op < minstr->getNumOperands(); op++)
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{
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const MachineOperand& mop = minstr->getOperand(op);
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// skip the result position (for efficiency below) and any other
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// positions already marked as not a virtual register
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if (instrDesc.resultPos == (int) op ||
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mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
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mop.getVRegValue() == NULL)
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{
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continue;
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}
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Value* opValue = mop.getVRegValue();
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bool constantThatMustBeLoaded = false;
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if (isa<ConstPoolVal>(opValue))
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{
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unsigned int machineRegNum;
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int64_t immedValue;
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MachineOperand::MachineOperandType opType =
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ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
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/*canUseImmed*/ (op == 1),
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machineRegNum, immedValue);
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if (opType == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperand(op, machineRegNum);
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else if (opType == MachineOperand::MO_VirtualRegister)
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constantThatMustBeLoaded = true; // load is generated below
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else
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minstr->SetMachineOperand(op, opType, immedValue);
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}
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if (constantThatMustBeLoaded || isa<GlobalValue>(opValue))
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{ // opValue is a constant that must be explicitly loaded into a reg.
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TmpInstruction* tmpReg = InsertCodeToLoadConstant(opValue, vmInstr,
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loadConstVec, target);
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minstr->SetMachineOperand(op, MachineOperand::MO_VirtualRegister,
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tmpReg);
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}
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}
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//
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// Also, check for implicit operands used (not those defined) by the
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// machine instruction. These include:
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// -- arguments to a Call
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// -- return value of a Return
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// Any such operand that is a constant value needs to be fixed also.
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// The current instructions with implicit refs (viz., Call and Return)
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// have no immediate fields, so the constant always needs to be loaded
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// into a register.
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//
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for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
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if (isa<ConstPoolVal>(minstr->getImplicitRef(i)) ||
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isa<GlobalValue>(minstr->getImplicitRef(i)))
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{
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TmpInstruction* tmpReg =
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InsertCodeToLoadConstant(minstr->getImplicitRef(i), vmInstr,
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loadConstVec, target);
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minstr->setImplicitRef(i, tmpReg);
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}
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return loadConstVec;
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}
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#undef SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
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#ifdef SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
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unsigned
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FixConstantOperands(const InstructionNode* vmInstrNode,
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TargetMachine& target)
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{
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Instruction* vmInstr = vmInstrNode->getInstruction();
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MachineCodeForVMInstr& mvec = vmInstr->getMachineInstrVec();
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for (unsigned i=0; i < mvec.size(); i++)
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{
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vector<MachineInsr*> loadConstVec =
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FixConstantOperandsForInstr(mvec[i], target);
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}
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//
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// Finally, inserted the generated instructions in the vector
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// to be returned.
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//
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unsigned numNew = loadConstVec.size();
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if (numNew > 0)
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{
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// Insert the new instructions *before* the old ones by moving
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// the old ones over `numNew' positions (last-to-first, of course!).
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// We do check *after* returning that we did not exceed the vector mvec.
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for (int i=numInstr-1; i >= 0; i--)
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mvec[i+numNew] = mvec[i];
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for (unsigned i=0; i < numNew; i++)
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mvec[i] = loadConstVec[i];
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}
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return (numInstr + numNew);
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}
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#endif SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
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