mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-01 19:29:22 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72991 91177308-0d34-0410-b5e6-96231b3b80d8
8874 lines
344 KiB
C++
8874 lines
344 KiB
C++
//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86ISelLowering.h"
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#include "X86TargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
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// Forward declarations.
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static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
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SDValue V2);
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X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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: TargetLowering(TM) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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X86ScalarSSEf64 = Subtarget->hasSSE2();
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X86ScalarSSEf32 = Subtarget->hasSSE1();
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X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
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RegInfo = TM.getRegisterInfo();
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TD = getTargetData();
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// Set up the TargetLowering object.
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// X86 is weird, it always uses i8 for shift amounts and setcc results.
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setShiftAmountType(MVT::i8);
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setBooleanContents(ZeroOrOneBooleanContent);
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setSchedulingPreference(SchedulingForRegPressure);
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setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
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setStackPointerRegisterToSaveRestore(X86StackPtr);
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if (Subtarget->isTargetDarwin()) {
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// Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
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setUseUnderscoreSetJmp(false);
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setUseUnderscoreLongJmp(false);
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} else if (Subtarget->isTargetMingw()) {
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// MS runtime is weird: it exports _setjmp, but longjmp!
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setUseUnderscoreSetJmp(true);
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setUseUnderscoreLongJmp(false);
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} else {
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setUseUnderscoreSetJmp(true);
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setUseUnderscoreLongJmp(true);
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}
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// Set up the register classes.
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addRegisterClass(MVT::i8, X86::GR8RegisterClass);
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addRegisterClass(MVT::i16, X86::GR16RegisterClass);
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addRegisterClass(MVT::i32, X86::GR32RegisterClass);
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if (Subtarget->is64Bit())
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addRegisterClass(MVT::i64, X86::GR64RegisterClass);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// We don't accept any truncstore of integer registers.
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setTruncStoreAction(MVT::i64, MVT::i32, Expand);
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setTruncStoreAction(MVT::i64, MVT::i16, Expand);
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setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
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setTruncStoreAction(MVT::i32, MVT::i16, Expand);
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setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
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setTruncStoreAction(MVT::i16, MVT::i8, Expand);
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// SETOEQ and SETUNE require checking two conditions.
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setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
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setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
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setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
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setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
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setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
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setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
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// Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
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// operation.
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setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
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} else if (!UseSoftFloat) {
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if (X86ScalarSSEf64) {
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// We have an impenetrably clever algorithm for ui64->double only.
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setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
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}
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// We have an algorithm for SSE2, and we turn this into a 64-bit
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// FILD for other targets.
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setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
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}
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// Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
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// this operation.
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
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if (!UseSoftFloat) {
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// SSE has no i16 to fp conversion, only i32
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if (X86ScalarSSEf32) {
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
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// f32 and f64 cases are Legal, f80 case is not
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setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
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} else {
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
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setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
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}
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} else {
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
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}
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// In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
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// are Legal, f80 is custom lowered.
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setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
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setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
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// Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
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// this operation.
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setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
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setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
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if (X86ScalarSSEf32) {
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setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
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// f32 and f64 cases are Legal, f80 case is not
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setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
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} else {
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setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
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}
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// Handle FP_TO_UINT by promoting the destination to a larger signed
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// conversion.
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setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
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setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
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setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
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} else if (!UseSoftFloat) {
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if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
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// Expand FP_TO_UINT into a select.
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// FIXME: We would like to use a Custom expander here eventually to do
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// the optimal thing for SSE vs. the default expansion in the legalizer.
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
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else
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// With SSE3 we can use fisttpll to convert to a signed i64; without
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// SSE, we're stuck with a fistpll.
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
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}
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// TODO: when we have SSE, these could be more efficient, by using movd/movq.
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if (!X86ScalarSSEf64) {
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setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
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setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
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}
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// Scalar integer divide and remainder are lowered to use operations that
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// produce two results, to match the available instructions. This exposes
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// the two-result form to trivial CSE, which is able to combine x/y and x%y
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// into a single instruction.
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//
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// Scalar integer multiply-high is also lowered to use two-result
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// operations, to match the available instructions. However, plain multiply
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// (low) operations are left as Legal, as there are single-result
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// instructions for this in x86. Using the two-result multiply instructions
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// when both high and low results are needed must be arranged by dagcombine.
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setOperationAction(ISD::MULHS , MVT::i8 , Expand);
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setOperationAction(ISD::MULHU , MVT::i8 , Expand);
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setOperationAction(ISD::SDIV , MVT::i8 , Expand);
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setOperationAction(ISD::UDIV , MVT::i8 , Expand);
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setOperationAction(ISD::SREM , MVT::i8 , Expand);
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setOperationAction(ISD::UREM , MVT::i8 , Expand);
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setOperationAction(ISD::MULHS , MVT::i16 , Expand);
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setOperationAction(ISD::MULHU , MVT::i16 , Expand);
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setOperationAction(ISD::SDIV , MVT::i16 , Expand);
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setOperationAction(ISD::UDIV , MVT::i16 , Expand);
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setOperationAction(ISD::SREM , MVT::i16 , Expand);
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setOperationAction(ISD::UREM , MVT::i16 , Expand);
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setOperationAction(ISD::MULHS , MVT::i32 , Expand);
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setOperationAction(ISD::MULHU , MVT::i32 , Expand);
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setOperationAction(ISD::SDIV , MVT::i32 , Expand);
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setOperationAction(ISD::UDIV , MVT::i32 , Expand);
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setOperationAction(ISD::SREM , MVT::i32 , Expand);
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setOperationAction(ISD::UREM , MVT::i32 , Expand);
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setOperationAction(ISD::MULHS , MVT::i64 , Expand);
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setOperationAction(ISD::MULHU , MVT::i64 , Expand);
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setOperationAction(ISD::SDIV , MVT::i64 , Expand);
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setOperationAction(ISD::UDIV , MVT::i64 , Expand);
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setOperationAction(ISD::SREM , MVT::i64 , Expand);
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setOperationAction(ISD::UREM , MVT::i64 , Expand);
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setOperationAction(ISD::BR_JT , MVT::Other, Expand);
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setOperationAction(ISD::BRCOND , MVT::Other, Custom);
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setOperationAction(ISD::BR_CC , MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
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if (Subtarget->is64Bit())
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setOperationAction(ISD::FREM , MVT::f32 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::FREM , MVT::f80 , Expand);
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setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
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}
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setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
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setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
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// These should be promoted to a larger select which is supported.
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setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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// X86 wants to expand cmov itself.
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setOperationAction(ISD::SELECT , MVT::i16 , Custom);
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setOperationAction(ISD::SELECT , MVT::i32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f32 , Custom);
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setOperationAction(ISD::SELECT , MVT::f64 , Custom);
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setOperationAction(ISD::SELECT , MVT::f80 , Custom);
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f64 , Custom);
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setOperationAction(ISD::SETCC , MVT::f80 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::SELECT , MVT::i64 , Custom);
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setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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}
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// X86 ret instruction may pop stack.
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setOperationAction(ISD::RET , MVT::Other, Custom);
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setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
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// Darwin ABI issue.
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setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
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setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
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setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
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if (Subtarget->is64Bit())
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
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setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
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setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
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}
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// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
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setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
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setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
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setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
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setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
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setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
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}
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if (Subtarget->hasSSE1())
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setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
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if (!Subtarget->hasSSE2())
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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// Expand certain atomics
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
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if (!Subtarget->is64Bit()) {
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setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
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}
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// Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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// FIXME - use subtarget debug flags
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if (!Subtarget->isTargetDarwin() &&
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!Subtarget->isTargetELF() &&
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!Subtarget->isTargetCygMing()) {
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setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
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}
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setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
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setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
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setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
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setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
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if (Subtarget->is64Bit()) {
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setExceptionPointerRegister(X86::RAX);
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setExceptionSelectorRegister(X86::RDX);
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} else {
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setExceptionPointerRegister(X86::EAX);
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setExceptionSelectorRegister(X86::EDX);
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}
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setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
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setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
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setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
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setOperationAction(ISD::TRAP, MVT::Other, Legal);
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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setOperationAction(ISD::VAEND , MVT::Other, Expand);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::VAARG , MVT::Other, Custom);
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setOperationAction(ISD::VACOPY , MVT::Other, Custom);
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} else {
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setOperationAction(ISD::VAARG , MVT::Other, Expand);
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setOperationAction(ISD::VACOPY , MVT::Other, Expand);
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}
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
|
|
if (Subtarget->is64Bit())
|
|
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
|
|
if (Subtarget->isTargetCygMing())
|
|
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
|
|
else
|
|
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
|
|
|
|
if (!UseSoftFloat && X86ScalarSSEf64) {
|
|
// f32 and f64 use SSE.
|
|
// Set up the FP register classes.
|
|
addRegisterClass(MVT::f32, X86::FR32RegisterClass);
|
|
addRegisterClass(MVT::f64, X86::FR64RegisterClass);
|
|
|
|
// Use ANDPD to simulate FABS.
|
|
setOperationAction(ISD::FABS , MVT::f64, Custom);
|
|
setOperationAction(ISD::FABS , MVT::f32, Custom);
|
|
|
|
// Use XORP to simulate FNEG.
|
|
setOperationAction(ISD::FNEG , MVT::f64, Custom);
|
|
setOperationAction(ISD::FNEG , MVT::f32, Custom);
|
|
|
|
// Use ANDPD and ORPD to simulate FCOPYSIGN.
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
|
|
|
|
// We don't support sin/cos/fmod
|
|
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
|
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
|
|
|
// Expand FP immediates into loads from the stack, except for the special
|
|
// cases we handle.
|
|
addLegalFPImmediate(APFloat(+0.0)); // xorpd
|
|
addLegalFPImmediate(APFloat(+0.0f)); // xorps
|
|
} else if (!UseSoftFloat && X86ScalarSSEf32) {
|
|
// Use SSE for f32, x87 for f64.
|
|
// Set up the FP register classes.
|
|
addRegisterClass(MVT::f32, X86::FR32RegisterClass);
|
|
addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
|
|
|
|
// Use ANDPS to simulate FABS.
|
|
setOperationAction(ISD::FABS , MVT::f32, Custom);
|
|
|
|
// Use XORP to simulate FNEG.
|
|
setOperationAction(ISD::FNEG , MVT::f32, Custom);
|
|
|
|
setOperationAction(ISD::UNDEF, MVT::f64, Expand);
|
|
|
|
// Use ANDPS and ORPS to simulate FCOPYSIGN.
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
|
|
|
|
// We don't support sin/cos/fmod
|
|
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
|
|
|
// Special cases we handle for FP constants.
|
|
addLegalFPImmediate(APFloat(+0.0f)); // xorps
|
|
addLegalFPImmediate(APFloat(+0.0)); // FLD0
|
|
addLegalFPImmediate(APFloat(+1.0)); // FLD1
|
|
addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
|
|
addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
|
|
|
|
if (!UnsafeFPMath) {
|
|
setOperationAction(ISD::FSIN , MVT::f64 , Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f64 , Expand);
|
|
}
|
|
} else if (!UseSoftFloat) {
|
|
// f32 and f64 in x87.
|
|
// Set up the FP register classes.
|
|
addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
|
|
addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
|
|
|
|
setOperationAction(ISD::UNDEF, MVT::f64, Expand);
|
|
setOperationAction(ISD::UNDEF, MVT::f32, Expand);
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
|
|
|
|
if (!UnsafeFPMath) {
|
|
setOperationAction(ISD::FSIN , MVT::f64 , Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f64 , Expand);
|
|
}
|
|
addLegalFPImmediate(APFloat(+0.0)); // FLD0
|
|
addLegalFPImmediate(APFloat(+1.0)); // FLD1
|
|
addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
|
|
addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
|
|
addLegalFPImmediate(APFloat(+0.0f)); // FLD0
|
|
addLegalFPImmediate(APFloat(+1.0f)); // FLD1
|
|
addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
|
|
addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
|
|
}
|
|
|
|
// Long double always uses X87.
|
|
if (!UseSoftFloat) {
|
|
addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
|
|
setOperationAction(ISD::UNDEF, MVT::f80, Expand);
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
|
|
{
|
|
bool ignored;
|
|
APFloat TmpFlt(+0.0);
|
|
TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
|
|
&ignored);
|
|
addLegalFPImmediate(TmpFlt); // FLD0
|
|
TmpFlt.changeSign();
|
|
addLegalFPImmediate(TmpFlt); // FLD0/FCHS
|
|
APFloat TmpFlt2(+1.0);
|
|
TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
|
|
&ignored);
|
|
addLegalFPImmediate(TmpFlt2); // FLD1
|
|
TmpFlt2.changeSign();
|
|
addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
|
|
}
|
|
|
|
if (!UnsafeFPMath) {
|
|
setOperationAction(ISD::FSIN , MVT::f80 , Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f80 , Expand);
|
|
}
|
|
}
|
|
|
|
// Always use a library call for pow.
|
|
setOperationAction(ISD::FPOW , MVT::f32 , Expand);
|
|
setOperationAction(ISD::FPOW , MVT::f64 , Expand);
|
|
setOperationAction(ISD::FPOW , MVT::f80 , Expand);
|
|
|
|
setOperationAction(ISD::FLOG, MVT::f80, Expand);
|
|
setOperationAction(ISD::FLOG2, MVT::f80, Expand);
|
|
setOperationAction(ISD::FLOG10, MVT::f80, Expand);
|
|
setOperationAction(ISD::FEXP, MVT::f80, Expand);
|
|
setOperationAction(ISD::FEXP2, MVT::f80, Expand);
|
|
|
|
// First set operation action for all vector types to either promote
|
|
// (for widening) or expand (for scalarization). Then we will selectively
|
|
// turn on ones that can be effectively codegen'd.
|
|
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
|
|
VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
|
|
setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
|
|
setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
|
|
setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
|
|
}
|
|
|
|
// FIXME: In order to prevent SSE instructions being expanded to MMX ones
|
|
// with -msoft-float, disable use of MMX as well.
|
|
if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
|
|
addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
|
|
addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
|
|
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
|
|
addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
|
|
addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
|
|
|
|
setOperationAction(ISD::ADD, MVT::v8i8, Legal);
|
|
setOperationAction(ISD::ADD, MVT::v4i16, Legal);
|
|
setOperationAction(ISD::ADD, MVT::v2i32, Legal);
|
|
setOperationAction(ISD::ADD, MVT::v1i64, Legal);
|
|
|
|
setOperationAction(ISD::SUB, MVT::v8i8, Legal);
|
|
setOperationAction(ISD::SUB, MVT::v4i16, Legal);
|
|
setOperationAction(ISD::SUB, MVT::v2i32, Legal);
|
|
setOperationAction(ISD::SUB, MVT::v1i64, Legal);
|
|
|
|
setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
|
|
setOperationAction(ISD::MUL, MVT::v4i16, Legal);
|
|
|
|
setOperationAction(ISD::AND, MVT::v8i8, Promote);
|
|
AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
|
|
setOperationAction(ISD::AND, MVT::v4i16, Promote);
|
|
AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
|
|
setOperationAction(ISD::AND, MVT::v2i32, Promote);
|
|
AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
|
|
setOperationAction(ISD::AND, MVT::v1i64, Legal);
|
|
|
|
setOperationAction(ISD::OR, MVT::v8i8, Promote);
|
|
AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
|
|
setOperationAction(ISD::OR, MVT::v4i16, Promote);
|
|
AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
|
|
setOperationAction(ISD::OR, MVT::v2i32, Promote);
|
|
AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
|
|
setOperationAction(ISD::OR, MVT::v1i64, Legal);
|
|
|
|
setOperationAction(ISD::XOR, MVT::v8i8, Promote);
|
|
AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
|
|
setOperationAction(ISD::XOR, MVT::v4i16, Promote);
|
|
AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
|
|
setOperationAction(ISD::XOR, MVT::v2i32, Promote);
|
|
AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
|
|
setOperationAction(ISD::XOR, MVT::v1i64, Legal);
|
|
|
|
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
|
|
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
|
|
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
|
|
AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
|
|
setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
|
|
AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
|
|
setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
|
|
AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
|
|
setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
|
|
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
|
|
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
|
|
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
|
|
|
|
setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
|
|
setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
|
|
setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
|
|
setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
|
|
setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
|
|
setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
|
|
}
|
|
|
|
if (!UseSoftFloat && Subtarget->hasSSE1()) {
|
|
addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
|
|
|
|
setOperationAction(ISD::FADD, MVT::v4f32, Legal);
|
|
setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
|
|
setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
|
|
setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
|
|
setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
|
|
setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
|
|
setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
|
|
setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
|
|
setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
|
|
}
|
|
|
|
if (!UseSoftFloat && Subtarget->hasSSE2()) {
|
|
addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
|
|
|
|
// FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
|
|
// registers cannot be used even for integer operations.
|
|
addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
|
|
addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
|
|
addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
|
|
addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
|
|
|
|
setOperationAction(ISD::ADD, MVT::v16i8, Legal);
|
|
setOperationAction(ISD::ADD, MVT::v8i16, Legal);
|
|
setOperationAction(ISD::ADD, MVT::v4i32, Legal);
|
|
setOperationAction(ISD::ADD, MVT::v2i64, Legal);
|
|
setOperationAction(ISD::MUL, MVT::v2i64, Custom);
|
|
setOperationAction(ISD::SUB, MVT::v16i8, Legal);
|
|
setOperationAction(ISD::SUB, MVT::v8i16, Legal);
|
|
setOperationAction(ISD::SUB, MVT::v4i32, Legal);
|
|
setOperationAction(ISD::SUB, MVT::v2i64, Legal);
|
|
setOperationAction(ISD::MUL, MVT::v8i16, Legal);
|
|
setOperationAction(ISD::FADD, MVT::v2f64, Legal);
|
|
setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
|
|
setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
|
|
setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
|
|
setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
|
|
setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
|
|
|
|
setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
|
|
setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
|
|
setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
|
|
setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
|
|
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
|
|
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
|
|
|
|
// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
|
|
for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
|
|
MVT VT = (MVT::SimpleValueType)i;
|
|
// Do not attempt to custom lower non-power-of-2 vectors
|
|
if (!isPowerOf2_32(VT.getVectorNumElements()))
|
|
continue;
|
|
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
|
|
}
|
|
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
|
|
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
|
|
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
|
|
|
|
if (Subtarget->is64Bit()) {
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
|
|
}
|
|
|
|
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
|
|
for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
|
|
setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
|
|
AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
|
|
setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
|
|
AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
|
|
setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
|
|
AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
|
|
setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
|
|
AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
|
|
setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
|
|
AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
|
|
}
|
|
|
|
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
|
|
|
|
// Custom lower v2i64 and v2f64 selects.
|
|
setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
|
|
setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
|
|
setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
|
|
setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
|
|
|
|
setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
|
|
setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
|
|
if (!DisableMMX && Subtarget->hasMMX()) {
|
|
setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
|
|
setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
|
|
}
|
|
}
|
|
|
|
if (Subtarget->hasSSE41()) {
|
|
// FIXME: Do we need to handle scalar-to-vector here?
|
|
setOperationAction(ISD::MUL, MVT::v4i32, Legal);
|
|
|
|
// i8 and i16 vectors are custom , because the source register and source
|
|
// source memory operand types are not the same width. f32 vectors are
|
|
// custom since the immediate controlling the insert encodes additional
|
|
// information.
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
|
|
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
|
|
|
|
if (Subtarget->is64Bit()) {
|
|
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
|
|
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
|
|
}
|
|
}
|
|
|
|
if (Subtarget->hasSSE42()) {
|
|
setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
|
|
}
|
|
|
|
// We want to custom lower some of our intrinsics.
|
|
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
|
|
|
|
// Add/Sub/Mul with overflow operations are custom lowered.
|
|
setOperationAction(ISD::SADDO, MVT::i32, Custom);
|
|
setOperationAction(ISD::SADDO, MVT::i64, Custom);
|
|
setOperationAction(ISD::UADDO, MVT::i32, Custom);
|
|
setOperationAction(ISD::UADDO, MVT::i64, Custom);
|
|
setOperationAction(ISD::SSUBO, MVT::i32, Custom);
|
|
setOperationAction(ISD::SSUBO, MVT::i64, Custom);
|
|
setOperationAction(ISD::USUBO, MVT::i32, Custom);
|
|
setOperationAction(ISD::USUBO, MVT::i64, Custom);
|
|
setOperationAction(ISD::SMULO, MVT::i32, Custom);
|
|
setOperationAction(ISD::SMULO, MVT::i64, Custom);
|
|
setOperationAction(ISD::UMULO, MVT::i32, Custom);
|
|
setOperationAction(ISD::UMULO, MVT::i64, Custom);
|
|
|
|
if (!Subtarget->is64Bit()) {
|
|
// These libcalls are not available in 32-bit.
|
|
setLibcallName(RTLIB::SHL_I128, 0);
|
|
setLibcallName(RTLIB::SRL_I128, 0);
|
|
setLibcallName(RTLIB::SRA_I128, 0);
|
|
}
|
|
|
|
// We have target-specific dag combine patterns for the following nodes:
|
|
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
|
|
setTargetDAGCombine(ISD::BUILD_VECTOR);
|
|
setTargetDAGCombine(ISD::SELECT);
|
|
setTargetDAGCombine(ISD::SHL);
|
|
setTargetDAGCombine(ISD::SRA);
|
|
setTargetDAGCombine(ISD::SRL);
|
|
setTargetDAGCombine(ISD::STORE);
|
|
if (Subtarget->is64Bit())
|
|
setTargetDAGCombine(ISD::MUL);
|
|
|
|
computeRegisterProperties();
|
|
|
|
// FIXME: These should be based on subtarget info. Plus, the values should
|
|
// be smaller when we are in optimizing for size mode.
|
|
maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
|
|
maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
|
|
maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
|
|
allowUnalignedMemoryAccesses = true; // x86 supports it!
|
|
setPrefLoopAlignment(16);
|
|
benefitFromCodePlacementOpt = true;
|
|
}
|
|
|
|
|
|
MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
|
|
return MVT::i8;
|
|
}
|
|
|
|
|
|
/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
|
|
/// the desired ByVal argument alignment.
|
|
static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
|
|
if (MaxAlign == 16)
|
|
return;
|
|
if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
|
|
if (VTy->getBitWidth() == 128)
|
|
MaxAlign = 16;
|
|
} else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
|
|
unsigned EltAlign = 0;
|
|
getMaxByValAlign(ATy->getElementType(), EltAlign);
|
|
if (EltAlign > MaxAlign)
|
|
MaxAlign = EltAlign;
|
|
} else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
|
|
for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
|
|
unsigned EltAlign = 0;
|
|
getMaxByValAlign(STy->getElementType(i), EltAlign);
|
|
if (EltAlign > MaxAlign)
|
|
MaxAlign = EltAlign;
|
|
if (MaxAlign == 16)
|
|
break;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
|
/// function arguments in the caller parameter area. For X86, aggregates
|
|
/// that contain SSE vectors are placed at 16-byte boundaries while the rest
|
|
/// are at 4-byte boundaries.
|
|
unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
|
|
if (Subtarget->is64Bit()) {
|
|
// Max of 8 and alignment of type.
|
|
unsigned TyAlign = TD->getABITypeAlignment(Ty);
|
|
if (TyAlign > 8)
|
|
return TyAlign;
|
|
return 8;
|
|
}
|
|
|
|
unsigned Align = 4;
|
|
if (Subtarget->hasSSE1())
|
|
getMaxByValAlign(Ty, Align);
|
|
return Align;
|
|
}
|
|
|
|
/// getOptimalMemOpType - Returns the target specific optimal type for load
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
|
|
/// determining it.
|
|
MVT
|
|
X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
|
|
bool isSrcConst, bool isSrcStr,
|
|
SelectionDAG &DAG) const {
|
|
// FIXME: This turns off use of xmm stores for memset/memcpy on targets like
|
|
// linux. This is because the stack realignment code can't handle certain
|
|
// cases like PR2962. This should be removed when PR2962 is fixed.
|
|
const Function *F = DAG.getMachineFunction().getFunction();
|
|
bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
|
|
if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
|
|
if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
|
|
return MVT::v4i32;
|
|
if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
|
|
return MVT::v4f32;
|
|
}
|
|
if (Subtarget->is64Bit() && Size >= 8)
|
|
return MVT::i64;
|
|
return MVT::i32;
|
|
}
|
|
|
|
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
|
|
/// jumptable.
|
|
SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
|
|
SelectionDAG &DAG) const {
|
|
if (usesGlobalOffsetTable())
|
|
return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
|
|
if (!Subtarget->isPICStyleRIPRel())
|
|
// This doesn't have DebugLoc associated with it, but is not really the
|
|
// same as a Register.
|
|
return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
|
|
getPointerTy());
|
|
return Table;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Return Value Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "X86GenCallingConv.inc"
|
|
|
|
/// LowerRET - Lower an ISD::RET node.
|
|
SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
|
|
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
|
|
|
|
// If this is the first return lowered for this function, add the regs to the
|
|
// liveout set for the function.
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
|
if (RVLocs[i].isRegLoc())
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
|
}
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
// Handle tail call return.
|
|
Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
|
|
if (Chain.getOpcode() == X86ISD::TAILCALL) {
|
|
SDValue TailCall = Chain;
|
|
SDValue TargetAddress = TailCall.getOperand(1);
|
|
SDValue StackAdjustment = TailCall.getOperand(2);
|
|
assert(((TargetAddress.getOpcode() == ISD::Register &&
|
|
(cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
|
|
cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
|
|
TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
|
|
TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
|
|
"Expecting an global address, external symbol, or register");
|
|
assert(StackAdjustment.getOpcode() == ISD::Constant &&
|
|
"Expecting a const value");
|
|
|
|
SmallVector<SDValue,8> Operands;
|
|
Operands.push_back(Chain.getOperand(0));
|
|
Operands.push_back(TargetAddress);
|
|
Operands.push_back(StackAdjustment);
|
|
// Copy registers used by the call. Last operand is a flag so it is not
|
|
// copied.
|
|
for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
|
|
Operands.push_back(Chain.getOperand(i));
|
|
}
|
|
return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
|
|
Operands.size());
|
|
}
|
|
|
|
// Regular return.
|
|
SDValue Flag;
|
|
|
|
SmallVector<SDValue, 6> RetOps;
|
|
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
|
|
// Operand #1 = Bytes To Pop
|
|
RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
|
|
|
|
// Copy the result values into the output registers.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
CCValAssign &VA = RVLocs[i];
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
SDValue ValToCopy = Op.getOperand(i*2+1);
|
|
|
|
// Returns in ST0/ST1 are handled specially: these are pushed as operands to
|
|
// the RET instruction and handled by the FP Stackifier.
|
|
if (VA.getLocReg() == X86::ST0 ||
|
|
VA.getLocReg() == X86::ST1) {
|
|
// If this is a copy from an xmm register to ST(0), use an FPExtend to
|
|
// change the value to the FP stack register class.
|
|
if (isScalarFPTypeInSSEReg(VA.getValVT()))
|
|
ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
|
|
RetOps.push_back(ValToCopy);
|
|
// Don't emit a copytoreg.
|
|
continue;
|
|
}
|
|
|
|
// 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
|
|
// which is returned in RAX / RDX.
|
|
if (Subtarget->is64Bit()) {
|
|
MVT ValVT = ValToCopy.getValueType();
|
|
if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
|
|
ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
|
|
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
|
|
ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
|
|
}
|
|
}
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
|
|
Flag = Chain.getValue(1);
|
|
}
|
|
|
|
// The x86-64 ABI for returning structs by value requires that we copy
|
|
// the sret argument into %rax for the return. We saved the argument into
|
|
// a virtual register in the entry block, so now we copy the value out
|
|
// and into %rax.
|
|
if (Subtarget->is64Bit() &&
|
|
DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
|
unsigned Reg = FuncInfo->getSRetReturnReg();
|
|
if (!Reg) {
|
|
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
|
|
FuncInfo->setSRetReturnReg(Reg);
|
|
}
|
|
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
|
|
Flag = Chain.getValue(1);
|
|
}
|
|
|
|
RetOps[0] = Chain; // Update chain.
|
|
|
|
// Add the flag if we have it.
|
|
if (Flag.getNode())
|
|
RetOps.push_back(Flag);
|
|
|
|
return DAG.getNode(X86ISD::RET_FLAG, dl,
|
|
MVT::Other, &RetOps[0], RetOps.size());
|
|
}
|
|
|
|
|
|
/// LowerCallResult - Lower the result values of an ISD::CALL into the
|
|
/// appropriate copies out of appropriate physical registers. This assumes that
|
|
/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
|
|
/// being lowered. The returns a SDNode with the same number of values as the
|
|
/// ISD::CALL.
|
|
SDNode *X86TargetLowering::
|
|
LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
|
|
unsigned CallingConv, SelectionDAG &DAG) {
|
|
|
|
DebugLoc dl = TheCall->getDebugLoc();
|
|
// Assign locations to each value returned by this call.
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
bool isVarArg = TheCall->isVarArg();
|
|
bool Is64Bit = Subtarget->is64Bit();
|
|
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
|
|
CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
|
|
|
|
SmallVector<SDValue, 8> ResultVals;
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
CCValAssign &VA = RVLocs[i];
|
|
MVT CopyVT = VA.getValVT();
|
|
|
|
// If this is x86-64, and we disabled SSE, we can't return FP values
|
|
if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
|
|
((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
|
|
cerr << "SSE register return with SSE disabled\n";
|
|
exit(1);
|
|
}
|
|
|
|
// If this is a call to a function that returns an fp value on the floating
|
|
// point stack, but where we prefer to use the value in xmm registers, copy
|
|
// it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
|
|
if ((VA.getLocReg() == X86::ST0 ||
|
|
VA.getLocReg() == X86::ST1) &&
|
|
isScalarFPTypeInSSEReg(VA.getValVT())) {
|
|
CopyVT = MVT::f80;
|
|
}
|
|
|
|
SDValue Val;
|
|
if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
|
|
// For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
|
|
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
|
|
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
|
|
MVT::v2i64, InFlag).getValue(1);
|
|
Val = Chain.getValue(0);
|
|
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
|
|
Val, DAG.getConstant(0, MVT::i64));
|
|
} else {
|
|
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
|
|
MVT::i64, InFlag).getValue(1);
|
|
Val = Chain.getValue(0);
|
|
}
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
|
|
} else {
|
|
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
|
|
CopyVT, InFlag).getValue(1);
|
|
Val = Chain.getValue(0);
|
|
}
|
|
InFlag = Chain.getValue(2);
|
|
|
|
if (CopyVT != VA.getValVT()) {
|
|
// Round the F80 the right size, which also moves to the appropriate xmm
|
|
// register.
|
|
Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
|
|
// This truncation won't change the value.
|
|
DAG.getIntPtrConstant(1));
|
|
}
|
|
|
|
ResultVals.push_back(Val);
|
|
}
|
|
|
|
// Merge everything together with a MERGE_VALUES node.
|
|
ResultVals.push_back(Chain);
|
|
return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
|
|
&ResultVals[0], ResultVals.size()).getNode();
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// C & StdCall & Fast Calling Convention implementation
|
|
//===----------------------------------------------------------------------===//
|
|
// StdCall calling convention seems to be standard for many Windows' API
|
|
// routines and around. It differs from C calling convention just a little:
|
|
// callee should clean up the stack, not caller. Symbols should be also
|
|
// decorated in some fancy way :) It doesn't support any vector arguments.
|
|
// For info on fast calling convention see Fast Calling Convention (tail call)
|
|
// implementation LowerX86_32FastCCCallTo.
|
|
|
|
/// CallIsStructReturn - Determines whether a CALL node uses struct return
|
|
/// semantics.
|
|
static bool CallIsStructReturn(CallSDNode *TheCall) {
|
|
unsigned NumOps = TheCall->getNumArgs();
|
|
if (!NumOps)
|
|
return false;
|
|
|
|
return TheCall->getArgFlags(0).isSRet();
|
|
}
|
|
|
|
/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
|
|
/// return semantics.
|
|
static bool ArgsAreStructReturn(SDValue Op) {
|
|
unsigned NumArgs = Op.getNode()->getNumValues() - 1;
|
|
if (!NumArgs)
|
|
return false;
|
|
|
|
return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
|
|
}
|
|
|
|
/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
|
|
/// the callee to pop its own arguments. Callee pop is necessary to support tail
|
|
/// calls.
|
|
bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
|
|
if (IsVarArg)
|
|
return false;
|
|
|
|
switch (CallingConv) {
|
|
default:
|
|
return false;
|
|
case CallingConv::X86_StdCall:
|
|
return !Subtarget->is64Bit();
|
|
case CallingConv::X86_FastCall:
|
|
return !Subtarget->is64Bit();
|
|
case CallingConv::Fast:
|
|
return PerformTailCallOpt;
|
|
}
|
|
}
|
|
|
|
/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
|
|
/// given CallingConvention value.
|
|
CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
|
|
if (Subtarget->is64Bit()) {
|
|
if (Subtarget->isTargetWin64())
|
|
return CC_X86_Win64_C;
|
|
else if (CC == CallingConv::Fast && PerformTailCallOpt)
|
|
return CC_X86_64_TailCall;
|
|
else
|
|
return CC_X86_64_C;
|
|
}
|
|
|
|
if (CC == CallingConv::X86_FastCall)
|
|
return CC_X86_32_FastCall;
|
|
else if (CC == CallingConv::Fast)
|
|
return CC_X86_32_FastCC;
|
|
else
|
|
return CC_X86_32_C;
|
|
}
|
|
|
|
/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
|
|
/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
|
|
NameDecorationStyle
|
|
X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
|
|
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
|
if (CC == CallingConv::X86_FastCall)
|
|
return FastCall;
|
|
else if (CC == CallingConv::X86_StdCall)
|
|
return StdCall;
|
|
return None;
|
|
}
|
|
|
|
|
|
/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
|
|
/// in a register before calling.
|
|
bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
|
|
return !IsTailCall && !Is64Bit &&
|
|
getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
|
|
Subtarget->isPICStyleGOT();
|
|
}
|
|
|
|
/// CallRequiresFnAddressInReg - Check whether the call requires the function
|
|
/// address to be loaded in a register.
|
|
bool
|
|
X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
|
|
return !Is64Bit && IsTailCall &&
|
|
getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
|
|
Subtarget->isPICStyleGOT();
|
|
}
|
|
|
|
/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
|
|
/// by "Src" to address "Dst" with size and alignment information specified by
|
|
/// the specific parameter attribute. The copy will be passed as a byval
|
|
/// function parameter.
|
|
static SDValue
|
|
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
|
|
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
|
|
DebugLoc dl) {
|
|
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
|
|
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
|
|
/*AlwaysInline=*/true, NULL, 0, NULL, 0);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
|
|
const CCValAssign &VA,
|
|
MachineFrameInfo *MFI,
|
|
unsigned CC,
|
|
SDValue Root, unsigned i) {
|
|
// Create the nodes corresponding to a load from this parameter slot.
|
|
ISD::ArgFlagsTy Flags =
|
|
cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
|
|
bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
|
|
bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
|
|
|
|
// FIXME: For now, all byval parameter objects are marked mutable. This can be
|
|
// changed with more analysis.
|
|
// In case of tail call optimization mark all arguments mutable. Since they
|
|
// could be overwritten by lowering of arguments in case of a tail call.
|
|
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
|
|
VA.getLocMemOffset(), isImmutable);
|
|
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
|
|
if (Flags.isByVal())
|
|
return FIN;
|
|
return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
|
|
PseudoSourceValue::getFixedStack(FI), 0);
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
const Function* Fn = MF.getFunction();
|
|
if (Fn->hasExternalLinkage() &&
|
|
Subtarget->isTargetCygMing() &&
|
|
Fn->getName() == "main")
|
|
FuncInfo->setForceFramePointer(true);
|
|
|
|
// Decorate the function name.
|
|
FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
SDValue Root = Op.getOperand(0);
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
|
|
unsigned CC = MF.getFunction()->getCallingConv();
|
|
bool Is64Bit = Subtarget->is64Bit();
|
|
bool IsWin64 = Subtarget->isTargetWin64();
|
|
|
|
assert(!(isVarArg && CC == CallingConv::Fast) &&
|
|
"Var args not supported with calling convention fastcc");
|
|
|
|
// Assign locations to all of the incoming arguments.
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
|
|
CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
|
|
|
|
SmallVector<SDValue, 8> ArgValues;
|
|
unsigned LastVal = ~0U;
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
CCValAssign &VA = ArgLocs[i];
|
|
// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
|
|
// places.
|
|
assert(VA.getValNo() != LastVal &&
|
|
"Don't support value assigned to multiple locs yet");
|
|
LastVal = VA.getValNo();
|
|
|
|
if (VA.isRegLoc()) {
|
|
MVT RegVT = VA.getLocVT();
|
|
TargetRegisterClass *RC = NULL;
|
|
if (RegVT == MVT::i32)
|
|
RC = X86::GR32RegisterClass;
|
|
else if (Is64Bit && RegVT == MVT::i64)
|
|
RC = X86::GR64RegisterClass;
|
|
else if (RegVT == MVT::f32)
|
|
RC = X86::FR32RegisterClass;
|
|
else if (RegVT == MVT::f64)
|
|
RC = X86::FR64RegisterClass;
|
|
else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
|
|
RC = X86::VR128RegisterClass;
|
|
else if (RegVT.isVector()) {
|
|
assert(RegVT.getSizeInBits() == 64);
|
|
if (!Is64Bit)
|
|
RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
|
|
else {
|
|
// Darwin calling convention passes MMX values in either GPRs or
|
|
// XMMs in x86-64. Other targets pass them in memory.
|
|
if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
|
|
RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
|
|
RegVT = MVT::v2i64;
|
|
} else {
|
|
RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
|
|
RegVT = MVT::i64;
|
|
}
|
|
}
|
|
} else {
|
|
assert(0 && "Unknown argument type!");
|
|
}
|
|
|
|
unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
|
|
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
|
|
|
|
// If this is an 8 or 16-bit value, it is really passed promoted to 32
|
|
// bits. Insert an assert[sz]ext to capture this, then truncate to the
|
|
// right size.
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
|
|
|
|
// Handle MMX values passed in GPRs.
|
|
if (Is64Bit && RegVT != VA.getLocVT()) {
|
|
if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
|
|
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
|
|
else if (RC == X86::VR128RegisterClass) {
|
|
ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
|
|
ArgValue, DAG.getConstant(0, MVT::i64));
|
|
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
|
|
}
|
|
}
|
|
|
|
ArgValues.push_back(ArgValue);
|
|
} else {
|
|
assert(VA.isMemLoc());
|
|
ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
|
|
}
|
|
}
|
|
|
|
// The x86-64 ABI for returning structs by value requires that we copy
|
|
// the sret argument into %rax for the return. Save the argument into
|
|
// a virtual register so that we can access it from the return points.
|
|
if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
|
unsigned Reg = FuncInfo->getSRetReturnReg();
|
|
if (!Reg) {
|
|
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
|
|
FuncInfo->setSRetReturnReg(Reg);
|
|
}
|
|
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
|
|
Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
|
|
}
|
|
|
|
unsigned StackSize = CCInfo.getNextStackOffset();
|
|
// align stack specially for tail calls
|
|
if (PerformTailCallOpt && CC == CallingConv::Fast)
|
|
StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
|
|
|
|
// If the function takes variable number of arguments, make a frame index for
|
|
// the start of the first vararg value... for expansion of llvm.va_start.
|
|
if (isVarArg) {
|
|
if (Is64Bit || CC != CallingConv::X86_FastCall) {
|
|
VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
|
|
}
|
|
if (Is64Bit) {
|
|
unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
|
|
|
|
// FIXME: We should really autogenerate these arrays
|
|
static const unsigned GPR64ArgRegsWin64[] = {
|
|
X86::RCX, X86::RDX, X86::R8, X86::R9
|
|
};
|
|
static const unsigned XMMArgRegsWin64[] = {
|
|
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
|
|
};
|
|
static const unsigned GPR64ArgRegs64Bit[] = {
|
|
X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
|
|
};
|
|
static const unsigned XMMArgRegs64Bit[] = {
|
|
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
|
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
|
};
|
|
const unsigned *GPR64ArgRegs, *XMMArgRegs;
|
|
|
|
if (IsWin64) {
|
|
TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
|
|
GPR64ArgRegs = GPR64ArgRegsWin64;
|
|
XMMArgRegs = XMMArgRegsWin64;
|
|
} else {
|
|
TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
|
|
GPR64ArgRegs = GPR64ArgRegs64Bit;
|
|
XMMArgRegs = XMMArgRegs64Bit;
|
|
}
|
|
unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
|
|
TotalNumIntRegs);
|
|
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
|
|
TotalNumXMMRegs);
|
|
|
|
bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
|
|
assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
|
|
"SSE register cannot be used when SSE is disabled!");
|
|
assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
|
|
"SSE register cannot be used when SSE is disabled!");
|
|
if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
|
|
// Kernel mode asks for SSE to be disabled, so don't push them
|
|
// on the stack.
|
|
TotalNumXMMRegs = 0;
|
|
|
|
// For X86-64, if there are vararg parameters that are passed via
|
|
// registers, then we must store them to their spots on the stack so they
|
|
// may be loaded by deferencing the result of va_next.
|
|
VarArgsGPOffset = NumIntRegs * 8;
|
|
VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
|
|
RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
|
|
TotalNumXMMRegs * 16, 16);
|
|
|
|
// Store the integer parameter registers.
|
|
SmallVector<SDValue, 8> MemOps;
|
|
SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
|
SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
|
|
DAG.getIntPtrConstant(VarArgsGPOffset));
|
|
for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
|
|
unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
|
|
X86::GR64RegisterClass);
|
|
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
|
|
SDValue Store =
|
|
DAG.getStore(Val.getValue(1), dl, Val, FIN,
|
|
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
|
|
MemOps.push_back(Store);
|
|
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
|
|
DAG.getIntPtrConstant(8));
|
|
}
|
|
|
|
// Now store the XMM (fp + vector) parameter registers.
|
|
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
|
|
DAG.getIntPtrConstant(VarArgsFPOffset));
|
|
for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
|
|
unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
|
|
X86::VR128RegisterClass);
|
|
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
|
|
SDValue Store =
|
|
DAG.getStore(Val.getValue(1), dl, Val, FIN,
|
|
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
|
|
MemOps.push_back(Store);
|
|
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
|
|
DAG.getIntPtrConstant(16));
|
|
}
|
|
if (!MemOps.empty())
|
|
Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&MemOps[0], MemOps.size());
|
|
}
|
|
}
|
|
|
|
ArgValues.push_back(Root);
|
|
|
|
// Some CCs need callee pop.
|
|
if (IsCalleePop(isVarArg, CC)) {
|
|
BytesToPopOnReturn = StackSize; // Callee pops everything.
|
|
BytesCallerReserves = 0;
|
|
} else {
|
|
BytesToPopOnReturn = 0; // Callee pops nothing.
|
|
// If this is an sret function, the return should pop the hidden pointer.
|
|
if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
|
|
BytesToPopOnReturn = 4;
|
|
BytesCallerReserves = StackSize;
|
|
}
|
|
|
|
if (!Is64Bit) {
|
|
RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
|
|
if (CC == CallingConv::X86_FastCall)
|
|
VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
|
|
}
|
|
|
|
FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
|
|
|
|
// Return the new list of results.
|
|
return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
|
|
&ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
|
|
const SDValue &StackPtr,
|
|
const CCValAssign &VA,
|
|
SDValue Chain,
|
|
SDValue Arg, ISD::ArgFlagsTy Flags) {
|
|
DebugLoc dl = TheCall->getDebugLoc();
|
|
unsigned LocMemOffset = VA.getLocMemOffset();
|
|
SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
|
|
PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
|
|
if (Flags.isByVal()) {
|
|
return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
|
|
}
|
|
return DAG.getStore(Chain, dl, Arg, PtrOff,
|
|
PseudoSourceValue::getStack(), LocMemOffset);
|
|
}
|
|
|
|
/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
|
|
/// optimization is performed and it is required.
|
|
SDValue
|
|
X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
|
|
SDValue &OutRetAddr,
|
|
SDValue Chain,
|
|
bool IsTailCall,
|
|
bool Is64Bit,
|
|
int FPDiff,
|
|
DebugLoc dl) {
|
|
if (!IsTailCall || FPDiff==0) return Chain;
|
|
|
|
// Adjust the Return address stack slot.
|
|
MVT VT = getPointerTy();
|
|
OutRetAddr = getReturnAddressFrameIndex(DAG);
|
|
|
|
// Load the "old" Return address.
|
|
OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
|
|
return SDValue(OutRetAddr.getNode(), 1);
|
|
}
|
|
|
|
/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
|
|
/// optimization is performed and it is required (FPDiff!=0).
|
|
static SDValue
|
|
EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
|
|
SDValue Chain, SDValue RetAddrFrIdx,
|
|
bool Is64Bit, int FPDiff, DebugLoc dl) {
|
|
// Store the return address to the appropriate stack slot.
|
|
if (!FPDiff) return Chain;
|
|
// Calculate the new stack slot for the return address.
|
|
int SlotSize = Is64Bit ? 8 : 4;
|
|
int NewReturnAddrFI =
|
|
MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
|
|
MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
|
|
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
|
|
Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
|
|
PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
|
|
return Chain;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
|
|
SDValue Chain = TheCall->getChain();
|
|
unsigned CC = TheCall->getCallingConv();
|
|
bool isVarArg = TheCall->isVarArg();
|
|
bool IsTailCall = TheCall->isTailCall() &&
|
|
CC == CallingConv::Fast && PerformTailCallOpt;
|
|
SDValue Callee = TheCall->getCallee();
|
|
bool Is64Bit = Subtarget->is64Bit();
|
|
bool IsStructRet = CallIsStructReturn(TheCall);
|
|
DebugLoc dl = TheCall->getDebugLoc();
|
|
|
|
assert(!(isVarArg && CC == CallingConv::Fast) &&
|
|
"Var args not supported with calling convention fastcc");
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
|
|
CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
|
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
|
if (PerformTailCallOpt && CC == CallingConv::Fast)
|
|
NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
|
|
|
|
int FPDiff = 0;
|
|
if (IsTailCall) {
|
|
// Lower arguments at fp - stackoffset + fpdiff.
|
|
unsigned NumBytesCallerPushed =
|
|
MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
|
|
FPDiff = NumBytesCallerPushed - NumBytes;
|
|
|
|
// Set the delta of movement of the returnaddr stackslot.
|
|
// But only set if delta is greater than previous delta.
|
|
if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
|
|
MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
|
|
}
|
|
|
|
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
|
|
|
|
SDValue RetAddrFrIdx;
|
|
// Load return adress for tail calls.
|
|
Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
|
|
FPDiff, dl);
|
|
|
|
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
|
|
SmallVector<SDValue, 8> MemOpChains;
|
|
SDValue StackPtr;
|
|
|
|
// Walk the register/memloc assignments, inserting copies/loads. In the case
|
|
// of tail call optimization arguments are handle later.
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
CCValAssign &VA = ArgLocs[i];
|
|
SDValue Arg = TheCall->getArg(i);
|
|
ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
|
|
bool isByVal = Flags.isByVal();
|
|
|
|
// Promote the value if needed.
|
|
switch (VA.getLocInfo()) {
|
|
default: assert(0 && "Unknown loc info!");
|
|
case CCValAssign::Full: break;
|
|
case CCValAssign::SExt:
|
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
|
|
break;
|
|
case CCValAssign::ZExt:
|
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
|
|
break;
|
|
case CCValAssign::AExt:
|
|
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
|
|
break;
|
|
}
|
|
|
|
if (VA.isRegLoc()) {
|
|
if (Is64Bit) {
|
|
MVT RegVT = VA.getLocVT();
|
|
if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
|
|
switch (VA.getLocReg()) {
|
|
default:
|
|
break;
|
|
case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
|
|
case X86::R8: {
|
|
// Special case: passing MMX values in GPR registers.
|
|
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
|
|
break;
|
|
}
|
|
case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
|
|
case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
|
|
// Special case: passing MMX values in XMM registers.
|
|
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
|
|
Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
|
|
Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
|
} else {
|
|
if (!IsTailCall || (IsTailCall && isByVal)) {
|
|
assert(VA.isMemLoc());
|
|
if (StackPtr.getNode() == 0)
|
|
StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
|
|
|
|
MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
|
|
Chain, Arg, Flags));
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!MemOpChains.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
|
// and flag operands which copy the outgoing args into registers.
|
|
SDValue InFlag;
|
|
// Tail call byval lowering might overwrite argument registers so in case of
|
|
// tail call optimization the copies to registers are lowered later.
|
|
if (!IsTailCall)
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
|
RegsToPass[i].second, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// ELF / PIC requires GOT in the EBX register before function calls via PLT
|
|
// GOT pointer.
|
|
if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
|
|
Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
|
|
DAG.getNode(X86ISD::GlobalBaseReg,
|
|
DebugLoc::getUnknownLoc(),
|
|
getPointerTy()),
|
|
InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
// If we are tail calling and generating PIC/GOT style code load the address
|
|
// of the callee into ecx. The value in ecx is used as target of the tail
|
|
// jump. This is done to circumvent the ebx/callee-saved problem for tail
|
|
// calls on PIC/GOT architectures. Normally we would just put the address of
|
|
// GOT into ebx and then call target@PLT. But for tail callss ebx would be
|
|
// restored (since ebx is callee saved) before jumping to the target@PLT.
|
|
if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
|
|
// Note: The actual moving to ecx is done further down.
|
|
GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
|
|
if (G && !G->getGlobal()->hasHiddenVisibility() &&
|
|
!G->getGlobal()->hasProtectedVisibility())
|
|
Callee = LowerGlobalAddress(Callee, DAG);
|
|
else if (isa<ExternalSymbolSDNode>(Callee))
|
|
Callee = LowerExternalSymbol(Callee,DAG);
|
|
}
|
|
|
|
if (Is64Bit && isVarArg) {
|
|
// From AMD64 ABI document:
|
|
// For calls that may call functions that use varargs or stdargs
|
|
// (prototype-less calls or calls to functions containing ellipsis (...) in
|
|
// the declaration) %al is used as hidden argument to specify the number
|
|
// of SSE registers used. The contents of %al do not need to match exactly
|
|
// the number of registers, but must be an ubound on the number of SSE
|
|
// registers used and is in the range 0 - 8 inclusive.
|
|
|
|
// FIXME: Verify this on Win64
|
|
// Count the number of XMM registers allocated.
|
|
static const unsigned XMMArgRegs[] = {
|
|
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
|
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
|
};
|
|
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
|
|
assert((Subtarget->hasSSE1() || !NumXMMRegs)
|
|
&& "SSE registers cannot be used when SSE is disabled");
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
|
|
DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
|
|
// For tail calls lower the arguments to the 'real' stack slot.
|
|
if (IsTailCall) {
|
|
SmallVector<SDValue, 8> MemOpChains2;
|
|
SDValue FIN;
|
|
int FI = 0;
|
|
// Do not flag preceeding copytoreg stuff together with the following stuff.
|
|
InFlag = SDValue();
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
CCValAssign &VA = ArgLocs[i];
|
|
if (!VA.isRegLoc()) {
|
|
assert(VA.isMemLoc());
|
|
SDValue Arg = TheCall->getArg(i);
|
|
ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
|
|
// Create frame index.
|
|
int32_t Offset = VA.getLocMemOffset()+FPDiff;
|
|
uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
|
|
FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
|
|
FIN = DAG.getFrameIndex(FI, getPointerTy());
|
|
|
|
if (Flags.isByVal()) {
|
|
// Copy relative to framepointer.
|
|
SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
|
|
if (StackPtr.getNode() == 0)
|
|
StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
|
|
getPointerTy());
|
|
Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
|
|
|
|
MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
|
|
Flags, DAG, dl));
|
|
} else {
|
|
// Store relative to framepointer.
|
|
MemOpChains2.push_back(
|
|
DAG.getStore(Chain, dl, Arg, FIN,
|
|
PseudoSourceValue::getFixedStack(FI), 0));
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!MemOpChains2.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&MemOpChains2[0], MemOpChains2.size());
|
|
|
|
// Copy arguments to their registers.
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
|
RegsToPass[i].second, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
InFlag =SDValue();
|
|
|
|
// Store the return address to the appropriate stack slot.
|
|
Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
|
|
FPDiff, dl);
|
|
}
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
|
|
// We should use extra load for direct calls to dllimported functions in
|
|
// non-JIT mode.
|
|
if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
|
|
getTargetMachine(), true))
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
|
|
G->getOffset());
|
|
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
|
|
} else if (IsTailCall) {
|
|
unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl,
|
|
DAG.getRegister(Opc, getPointerTy()),
|
|
Callee,InFlag);
|
|
Callee = DAG.getRegister(Opc, getPointerTy());
|
|
// Add register as live out.
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
|
|
}
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SmallVector<SDValue, 8> Ops;
|
|
|
|
if (IsTailCall) {
|
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
|
DAG.getIntPtrConstant(0, true), InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
|
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
Ops.clear();
|
|
}
|
|
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(Callee);
|
|
|
|
if (IsTailCall)
|
|
Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
|
|
|
|
// Add argument registers to the end of the list so that they are known live
|
|
// into the call.
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
// Add an implicit use GOT pointer in EBX.
|
|
if (!IsTailCall && !Is64Bit &&
|
|
getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
|
|
Subtarget->isPICStyleGOT())
|
|
Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
|
|
|
|
// Add an implicit use of AL for x86 vararg functions.
|
|
if (Is64Bit && isVarArg)
|
|
Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
|
|
|
|
if (InFlag.getNode())
|
|
Ops.push_back(InFlag);
|
|
|
|
if (IsTailCall) {
|
|
assert(InFlag.getNode() &&
|
|
"Flag must be set. Depend on flag being set in LowerRET");
|
|
Chain = DAG.getNode(X86ISD::TAILCALL, dl,
|
|
TheCall->getVTList(), &Ops[0], Ops.size());
|
|
|
|
return SDValue(Chain.getNode(), Op.getResNo());
|
|
}
|
|
|
|
Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Create the CALLSEQ_END node.
|
|
unsigned NumBytesForCalleeToPush;
|
|
if (IsCalleePop(isVarArg, CC))
|
|
NumBytesForCalleeToPush = NumBytes; // Callee pops everything
|
|
else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
|
|
// If this is is a call to a struct-return function, the callee
|
|
// pops the hidden struct pointer, so we have to push it back.
|
|
// This is common for Darwin/X86, Linux & Mingw32 targets.
|
|
NumBytesForCalleeToPush = 4;
|
|
else
|
|
NumBytesForCalleeToPush = 0; // Callee pops nothing.
|
|
|
|
// Returns a flag for retval copy to use.
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
DAG.getIntPtrConstant(NumBytes, true),
|
|
DAG.getIntPtrConstant(NumBytesForCalleeToPush,
|
|
true),
|
|
InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
// return.
|
|
return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
|
|
Op.getResNo());
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Fast Calling Convention (tail call) implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Like std call, callee cleans arguments, convention except that ECX is
|
|
// reserved for storing the tail called function address. Only 2 registers are
|
|
// free for argument passing (inreg). Tail call optimization is performed
|
|
// provided:
|
|
// * tailcallopt is enabled
|
|
// * caller/callee are fastcc
|
|
// On X86_64 architecture with GOT-style position independent code only local
|
|
// (within module) calls are supported at the moment.
|
|
// To keep the stack aligned according to platform abi the function
|
|
// GetAlignedArgumentStackSize ensures that argument delta is always multiples
|
|
// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
|
|
// If a tail called function callee has more arguments than the caller the
|
|
// caller needs to make sure that there is room to move the RETADDR to. This is
|
|
// achieved by reserving an area the size of the argument delta right after the
|
|
// original REtADDR, but before the saved framepointer or the spilled registers
|
|
// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
|
|
// stack layout:
|
|
// arg1
|
|
// arg2
|
|
// RETADDR
|
|
// [ new RETADDR
|
|
// move area ]
|
|
// (possible EBP)
|
|
// ESI
|
|
// EDI
|
|
// local1 ..
|
|
|
|
/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
|
|
/// for a 16 byte align requirement.
|
|
unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
|
|
SelectionDAG& DAG) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetFrameInfo &TFI = *TM.getFrameInfo();
|
|
unsigned StackAlignment = TFI.getStackAlignment();
|
|
uint64_t AlignMask = StackAlignment - 1;
|
|
int64_t Offset = StackSize;
|
|
uint64_t SlotSize = TD->getPointerSize();
|
|
if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
|
|
// Number smaller than 12 so just add the difference.
|
|
Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
|
|
} else {
|
|
// Mask out lower bits, add stackalignment once plus the 12 bytes.
|
|
Offset = ((~AlignMask) & Offset) + StackAlignment +
|
|
(StackAlignment-SlotSize);
|
|
}
|
|
return Offset;
|
|
}
|
|
|
|
/// IsEligibleForTailCallElimination - Check to see whether the next instruction
|
|
/// following the call is a return. A function is eligible if caller/callee
|
|
/// calling conventions match, currently only fastcc supports tail calls, and
|
|
/// the function CALL is immediatly followed by a RET.
|
|
bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
|
|
SDValue Ret,
|
|
SelectionDAG& DAG) const {
|
|
if (!PerformTailCallOpt)
|
|
return false;
|
|
|
|
if (CheckTailCallReturnConstraints(TheCall, Ret)) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
unsigned CallerCC = MF.getFunction()->getCallingConv();
|
|
unsigned CalleeCC= TheCall->getCallingConv();
|
|
if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
|
|
SDValue Callee = TheCall->getCallee();
|
|
// On x86/32Bit PIC/GOT tail calls are supported.
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
|
|
!Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
|
|
return true;
|
|
|
|
// Can only do local tail calls (in same module, hidden or protected) on
|
|
// x86_64 PIC/GOT at the moment.
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
return G->getGlobal()->hasHiddenVisibility()
|
|
|| G->getGlobal()->hasProtectedVisibility();
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
FastISel *
|
|
X86TargetLowering::createFastISel(MachineFunction &mf,
|
|
MachineModuleInfo *mmo,
|
|
DwarfWriter *dw,
|
|
DenseMap<const Value *, unsigned> &vm,
|
|
DenseMap<const BasicBlock *,
|
|
MachineBasicBlock *> &bm,
|
|
DenseMap<const AllocaInst *, int> &am
|
|
#ifndef NDEBUG
|
|
, SmallSet<Instruction*, 8> &cil
|
|
#endif
|
|
) {
|
|
return X86::createFastISel(mf, mmo, dw, vm, bm, am
|
|
#ifndef NDEBUG
|
|
, cil
|
|
#endif
|
|
);
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Other Lowering Hooks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
|
int ReturnAddrIndex = FuncInfo->getRAIndex();
|
|
|
|
if (ReturnAddrIndex == 0) {
|
|
// Set up a frame object for the return address.
|
|
uint64_t SlotSize = TD->getPointerSize();
|
|
ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
|
|
FuncInfo->setRAIndex(ReturnAddrIndex);
|
|
}
|
|
|
|
return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
|
|
}
|
|
|
|
|
|
/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
|
|
/// specific condition code, returning the condition code and the LHS/RHS of the
|
|
/// comparison to make.
|
|
static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
|
|
SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
|
|
if (!isFP) {
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
|
|
if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
|
|
// X > -1 -> X == 0, jump !sign.
|
|
RHS = DAG.getConstant(0, RHS.getValueType());
|
|
return X86::COND_NS;
|
|
} else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
|
|
// X < 0 -> X == 0, jump on sign.
|
|
return X86::COND_S;
|
|
} else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
|
|
// X < 1 -> X <= 0
|
|
RHS = DAG.getConstant(0, RHS.getValueType());
|
|
return X86::COND_LE;
|
|
}
|
|
}
|
|
|
|
switch (SetCCOpcode) {
|
|
default: assert(0 && "Invalid integer condition!");
|
|
case ISD::SETEQ: return X86::COND_E;
|
|
case ISD::SETGT: return X86::COND_G;
|
|
case ISD::SETGE: return X86::COND_GE;
|
|
case ISD::SETLT: return X86::COND_L;
|
|
case ISD::SETLE: return X86::COND_LE;
|
|
case ISD::SETNE: return X86::COND_NE;
|
|
case ISD::SETULT: return X86::COND_B;
|
|
case ISD::SETUGT: return X86::COND_A;
|
|
case ISD::SETULE: return X86::COND_BE;
|
|
case ISD::SETUGE: return X86::COND_AE;
|
|
}
|
|
}
|
|
|
|
// First determine if it is required or is profitable to flip the operands.
|
|
|
|
// If LHS is a foldable load, but RHS is not, flip the condition.
|
|
if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
|
|
!(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
|
|
SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
|
|
std::swap(LHS, RHS);
|
|
}
|
|
|
|
switch (SetCCOpcode) {
|
|
default: break;
|
|
case ISD::SETOLT:
|
|
case ISD::SETOLE:
|
|
case ISD::SETUGT:
|
|
case ISD::SETUGE:
|
|
std::swap(LHS, RHS);
|
|
break;
|
|
}
|
|
|
|
// On a floating point condition, the flags are set as follows:
|
|
// ZF PF CF op
|
|
// 0 | 0 | 0 | X > Y
|
|
// 0 | 0 | 1 | X < Y
|
|
// 1 | 0 | 0 | X == Y
|
|
// 1 | 1 | 1 | unordered
|
|
switch (SetCCOpcode) {
|
|
default: assert(0 && "Condcode should be pre-legalized away");
|
|
case ISD::SETUEQ:
|
|
case ISD::SETEQ: return X86::COND_E;
|
|
case ISD::SETOLT: // flipped
|
|
case ISD::SETOGT:
|
|
case ISD::SETGT: return X86::COND_A;
|
|
case ISD::SETOLE: // flipped
|
|
case ISD::SETOGE:
|
|
case ISD::SETGE: return X86::COND_AE;
|
|
case ISD::SETUGT: // flipped
|
|
case ISD::SETULT:
|
|
case ISD::SETLT: return X86::COND_B;
|
|
case ISD::SETUGE: // flipped
|
|
case ISD::SETULE:
|
|
case ISD::SETLE: return X86::COND_BE;
|
|
case ISD::SETONE:
|
|
case ISD::SETNE: return X86::COND_NE;
|
|
case ISD::SETUO: return X86::COND_P;
|
|
case ISD::SETO: return X86::COND_NP;
|
|
}
|
|
}
|
|
|
|
/// hasFPCMov - is there a floating point cmov for the specific X86 condition
|
|
/// code. Current x86 isa includes the following FP cmov instructions:
|
|
/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
|
|
static bool hasFPCMov(unsigned X86CC) {
|
|
switch (X86CC) {
|
|
default:
|
|
return false;
|
|
case X86::COND_B:
|
|
case X86::COND_BE:
|
|
case X86::COND_E:
|
|
case X86::COND_P:
|
|
case X86::COND_A:
|
|
case X86::COND_AE:
|
|
case X86::COND_NE:
|
|
case X86::COND_NP:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
/// isUndefOrInRange - Return true if Val is undef or if its value falls within
|
|
/// the specified range (L, H].
|
|
static bool isUndefOrInRange(int Val, int Low, int Hi) {
|
|
return (Val < 0) || (Val >= Low && Val < Hi);
|
|
}
|
|
|
|
/// isUndefOrEqual - Val is either less than zero (undef) or equal to the
|
|
/// specified value.
|
|
static bool isUndefOrEqual(int Val, int CmpVal) {
|
|
if (Val < 0 || Val == CmpVal)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
|
|
/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
|
|
/// the second operand.
|
|
static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
|
|
return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
|
|
if (VT == MVT::v2f64 || VT == MVT::v2i64)
|
|
return (Mask[0] < 2 && Mask[1] < 2);
|
|
return false;
|
|
}
|
|
|
|
bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isPSHUFDMask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
|
|
/// is suitable for input to PSHUFHW.
|
|
static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
if (VT != MVT::v8i16)
|
|
return false;
|
|
|
|
// Lower quadword copied in order or undef.
|
|
for (int i = 0; i != 4; ++i)
|
|
if (Mask[i] >= 0 && Mask[i] != i)
|
|
return false;
|
|
|
|
// Upper quadword shuffled.
|
|
for (int i = 4; i != 8; ++i)
|
|
if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isPSHUFHWMask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
|
|
/// is suitable for input to PSHUFLW.
|
|
static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
if (VT != MVT::v8i16)
|
|
return false;
|
|
|
|
// Upper quadword copied in order.
|
|
for (int i = 4; i != 8; ++i)
|
|
if (Mask[i] >= 0 && Mask[i] != i)
|
|
return false;
|
|
|
|
// Lower quadword shuffled.
|
|
for (int i = 0; i != 4; ++i)
|
|
if (Mask[i] >= 4)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isPSHUFLWMask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to SHUFP*.
|
|
static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
int NumElems = VT.getVectorNumElements();
|
|
if (NumElems != 2 && NumElems != 4)
|
|
return false;
|
|
|
|
int Half = NumElems / 2;
|
|
for (int i = 0; i < Half; ++i)
|
|
if (!isUndefOrInRange(Mask[i], 0, NumElems))
|
|
return false;
|
|
for (int i = Half; i < NumElems; ++i)
|
|
if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isSHUFPMask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
|
|
/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
|
|
/// half elements to come from vector 1 (which would equal the dest.) and
|
|
/// the upper half to come from vector 2.
|
|
static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
int NumElems = VT.getVectorNumElements();
|
|
|
|
if (NumElems != 2 && NumElems != 4)
|
|
return false;
|
|
|
|
int Half = NumElems / 2;
|
|
for (int i = 0; i < Half; ++i)
|
|
if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
|
|
return false;
|
|
for (int i = Half; i < NumElems; ++i)
|
|
if (!isUndefOrInRange(Mask[i], 0, NumElems))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return isCommutedSHUFPMask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
|
|
bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
|
|
if (N->getValueType(0).getVectorNumElements() != 4)
|
|
return false;
|
|
|
|
// Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
|
|
return isUndefOrEqual(N->getMaskElt(0), 6) &&
|
|
isUndefOrEqual(N->getMaskElt(1), 7) &&
|
|
isUndefOrEqual(N->getMaskElt(2), 2) &&
|
|
isUndefOrEqual(N->getMaskElt(3), 3);
|
|
}
|
|
|
|
/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
|
|
bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
|
|
unsigned NumElems = N->getValueType(0).getVectorNumElements();
|
|
|
|
if (NumElems != 2 && NumElems != 4)
|
|
return false;
|
|
|
|
for (unsigned i = 0; i < NumElems/2; ++i)
|
|
if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
|
|
return false;
|
|
|
|
for (unsigned i = NumElems/2; i < NumElems; ++i)
|
|
if (!isUndefOrEqual(N->getMaskElt(i), i))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
|
|
/// and MOVLHPS.
|
|
bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
|
|
unsigned NumElems = N->getValueType(0).getVectorNumElements();
|
|
|
|
if (NumElems != 2 && NumElems != 4)
|
|
return false;
|
|
|
|
for (unsigned i = 0; i < NumElems/2; ++i)
|
|
if (!isUndefOrEqual(N->getMaskElt(i), i))
|
|
return false;
|
|
|
|
for (unsigned i = 0; i < NumElems/2; ++i)
|
|
if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
|
|
/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
|
|
/// <2, 3, 2, 3>
|
|
bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
|
|
unsigned NumElems = N->getValueType(0).getVectorNumElements();
|
|
|
|
if (NumElems != 4)
|
|
return false;
|
|
|
|
return isUndefOrEqual(N->getMaskElt(0), 2) &&
|
|
isUndefOrEqual(N->getMaskElt(1), 3) &&
|
|
isUndefOrEqual(N->getMaskElt(2), 2) &&
|
|
isUndefOrEqual(N->getMaskElt(3), 3);
|
|
}
|
|
|
|
/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to UNPCKL.
|
|
static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
|
|
bool V2IsSplat = false) {
|
|
int NumElts = VT.getVectorNumElements();
|
|
if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
|
|
return false;
|
|
|
|
for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
|
|
int BitI = Mask[i];
|
|
int BitI1 = Mask[i+1];
|
|
if (!isUndefOrEqual(BitI, j))
|
|
return false;
|
|
if (V2IsSplat) {
|
|
if (!isUndefOrEqual(BitI1, NumElts))
|
|
return false;
|
|
} else {
|
|
if (!isUndefOrEqual(BitI1, j + NumElts))
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
|
|
}
|
|
|
|
/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to UNPCKH.
|
|
static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT,
|
|
bool V2IsSplat = false) {
|
|
int NumElts = VT.getVectorNumElements();
|
|
if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
|
|
return false;
|
|
|
|
for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
|
|
int BitI = Mask[i];
|
|
int BitI1 = Mask[i+1];
|
|
if (!isUndefOrEqual(BitI, j + NumElts/2))
|
|
return false;
|
|
if (V2IsSplat) {
|
|
if (isUndefOrEqual(BitI1, NumElts))
|
|
return false;
|
|
} else {
|
|
if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
|
|
}
|
|
|
|
/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
|
|
/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
|
|
/// <0, 0, 1, 1>
|
|
static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
int NumElems = VT.getVectorNumElements();
|
|
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
|
|
return false;
|
|
|
|
for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
|
|
int BitI = Mask[i];
|
|
int BitI1 = Mask[i+1];
|
|
if (!isUndefOrEqual(BitI, j))
|
|
return false;
|
|
if (!isUndefOrEqual(BitI1, j))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
|
|
/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
|
|
/// <2, 2, 3, 3>
|
|
static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
int NumElems = VT.getVectorNumElements();
|
|
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
|
|
return false;
|
|
|
|
for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
|
|
int BitI = Mask[i];
|
|
int BitI1 = Mask[i+1];
|
|
if (!isUndefOrEqual(BitI, j))
|
|
return false;
|
|
if (!isUndefOrEqual(BitI1, j))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to MOVSS,
|
|
/// MOVSD, and MOVD, i.e. setting the lowest element.
|
|
static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
|
|
if (VT.getVectorElementType().getSizeInBits() < 32)
|
|
return false;
|
|
|
|
int NumElts = VT.getVectorNumElements();
|
|
|
|
if (!isUndefOrEqual(Mask[0], NumElts))
|
|
return false;
|
|
|
|
for (int i = 1; i < NumElts; ++i)
|
|
if (!isUndefOrEqual(Mask[i], i))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return ::isMOVLMask(M, N->getValueType(0));
|
|
}
|
|
|
|
/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
|
|
/// of what x86 movss want. X86 movs requires the lowest element to be lowest
|
|
/// element of vector 2 and the other elements to come from vector 1 in order.
|
|
static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
|
|
bool V2IsSplat = false, bool V2IsUndef = false) {
|
|
int NumOps = VT.getVectorNumElements();
|
|
if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
|
|
return false;
|
|
|
|
if (!isUndefOrEqual(Mask[0], 0))
|
|
return false;
|
|
|
|
for (int i = 1; i < NumOps; ++i)
|
|
if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
|
|
(V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
|
|
(V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
|
|
bool V2IsUndef = false) {
|
|
SmallVector<int, 8> M;
|
|
N->getMask(M);
|
|
return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
|
|
}
|
|
|
|
/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
|
|
bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
|
|
if (N->getValueType(0).getVectorNumElements() != 4)
|
|
return false;
|
|
|
|
// Expect 1, 1, 3, 3
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
int Elt = N->getMaskElt(i);
|
|
if (Elt >= 0 && Elt != 1)
|
|
return false;
|
|
}
|
|
|
|
bool HasHi = false;
|
|
for (unsigned i = 2; i < 4; ++i) {
|
|
int Elt = N->getMaskElt(i);
|
|
if (Elt >= 0 && Elt != 3)
|
|
return false;
|
|
if (Elt == 3)
|
|
HasHi = true;
|
|
}
|
|
// Don't use movshdup if it can be done with a shufps.
|
|
// FIXME: verify that matching u, u, 3, 3 is what we want.
|
|
return HasHi;
|
|
}
|
|
|
|
/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
|
|
bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
|
|
if (N->getValueType(0).getVectorNumElements() != 4)
|
|
return false;
|
|
|
|
// Expect 0, 0, 2, 2
|
|
for (unsigned i = 0; i < 2; ++i)
|
|
if (N->getMaskElt(i) > 0)
|
|
return false;
|
|
|
|
bool HasHi = false;
|
|
for (unsigned i = 2; i < 4; ++i) {
|
|
int Elt = N->getMaskElt(i);
|
|
if (Elt >= 0 && Elt != 2)
|
|
return false;
|
|
if (Elt == 2)
|
|
HasHi = true;
|
|
}
|
|
// Don't use movsldup if it can be done with a shufps.
|
|
return HasHi;
|
|
}
|
|
|
|
/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
/// specifies a shuffle of elements that is suitable for input to MOVDDUP.
|
|
bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
|
|
int e = N->getValueType(0).getVectorNumElements() / 2;
|
|
|
|
for (int i = 0; i < e; ++i)
|
|
if (!isUndefOrEqual(N->getMaskElt(i), i))
|
|
return false;
|
|
for (int i = 0; i < e; ++i)
|
|
if (!isUndefOrEqual(N->getMaskElt(e+i), i))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
|
|
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
|
|
/// instructions.
|
|
unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
|
|
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
|
|
int NumOperands = SVOp->getValueType(0).getVectorNumElements();
|
|
|
|
unsigned Shift = (NumOperands == 4) ? 2 : 1;
|
|
unsigned Mask = 0;
|
|
for (int i = 0; i < NumOperands; ++i) {
|
|
int Val = SVOp->getMaskElt(NumOperands-i-1);
|
|
if (Val < 0) Val = 0;
|
|
if (Val >= NumOperands) Val -= NumOperands;
|
|
Mask |= Val;
|
|
if (i != NumOperands - 1)
|
|
Mask <<= Shift;
|
|
}
|
|
return Mask;
|
|
}
|
|
|
|
/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
|
|
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
|
|
/// instructions.
|
|
unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
|
|
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
|
|
unsigned Mask = 0;
|
|
// 8 nodes, but we only care about the last 4.
|
|
for (unsigned i = 7; i >= 4; --i) {
|
|
int Val = SVOp->getMaskElt(i);
|
|
if (Val >= 0)
|
|
Mask |= (Val - 4);
|
|
if (i != 4)
|
|
Mask <<= 2;
|
|
}
|
|
return Mask;
|
|
}
|
|
|
|
/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
|
|
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
|
|
/// instructions.
|
|
unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
|
|
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
|
|
unsigned Mask = 0;
|
|
// 8 nodes, but we only care about the first 4.
|
|
for (int i = 3; i >= 0; --i) {
|
|
int Val = SVOp->getMaskElt(i);
|
|
if (Val >= 0)
|
|
Mask |= Val;
|
|
if (i != 0)
|
|
Mask <<= 2;
|
|
}
|
|
return Mask;
|
|
}
|
|
|
|
/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
|
|
/// their permute mask.
|
|
static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
|
|
SelectionDAG &DAG) {
|
|
MVT VT = SVOp->getValueType(0);
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
SmallVector<int, 8> MaskVec;
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
int idx = SVOp->getMaskElt(i);
|
|
if (idx < 0)
|
|
MaskVec.push_back(idx);
|
|
else if (idx < (int)NumElems)
|
|
MaskVec.push_back(idx + NumElems);
|
|
else
|
|
MaskVec.push_back(idx - NumElems);
|
|
}
|
|
return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
|
|
SVOp->getOperand(0), &MaskVec[0]);
|
|
}
|
|
|
|
/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
|
|
/// the two vector operands have swapped position.
|
|
static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
int idx = Mask[i];
|
|
if (idx < 0)
|
|
continue;
|
|
else if (idx < (int)NumElems)
|
|
Mask[i] = idx + NumElems;
|
|
else
|
|
Mask[i] = idx - NumElems;
|
|
}
|
|
}
|
|
|
|
/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
|
|
/// match movhlps. The lower half elements should come from upper half of
|
|
/// V1 (and in order), and the upper half elements should come from the upper
|
|
/// half of V2 (and in order).
|
|
static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
|
|
if (Op->getValueType(0).getVectorNumElements() != 4)
|
|
return false;
|
|
for (unsigned i = 0, e = 2; i != e; ++i)
|
|
if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
|
|
return false;
|
|
for (unsigned i = 2; i != 4; ++i)
|
|
if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
/// isScalarLoadToVector - Returns true if the node is a scalar load that
|
|
/// is promoted to a vector. It also returns the LoadSDNode by reference if
|
|
/// required.
|
|
static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
|
|
if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
|
|
return false;
|
|
N = N->getOperand(0).getNode();
|
|
if (!ISD::isNON_EXTLoad(N))
|
|
return false;
|
|
if (LD)
|
|
*LD = cast<LoadSDNode>(N);
|
|
return true;
|
|
}
|
|
|
|
/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
|
|
/// match movlp{s|d}. The lower half elements should come from lower half of
|
|
/// V1 (and in order), and the upper half elements should come from the upper
|
|
/// half of V2 (and in order). And since V1 will become the source of the
|
|
/// MOVLP, it must be either a vector load or a scalar load to vector.
|
|
static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
|
|
ShuffleVectorSDNode *Op) {
|
|
if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
|
|
return false;
|
|
// Is V2 is a vector load, don't do this transformation. We will try to use
|
|
// load folding shufps op.
|
|
if (ISD::isNON_EXTLoad(V2))
|
|
return false;
|
|
|
|
unsigned NumElems = Op->getValueType(0).getVectorNumElements();
|
|
|
|
if (NumElems != 2 && NumElems != 4)
|
|
return false;
|
|
for (unsigned i = 0, e = NumElems/2; i != e; ++i)
|
|
if (!isUndefOrEqual(Op->getMaskElt(i), i))
|
|
return false;
|
|
for (unsigned i = NumElems/2; i != NumElems; ++i)
|
|
if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
|
|
/// all the same.
|
|
static bool isSplatVector(SDNode *N) {
|
|
if (N->getOpcode() != ISD::BUILD_VECTOR)
|
|
return false;
|
|
|
|
SDValue SplatValue = N->getOperand(0);
|
|
for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
|
|
if (N->getOperand(i) != SplatValue)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
/// isZeroNode - Returns true if Elt is a constant zero or a floating point
|
|
/// constant +0.0.
|
|
static inline bool isZeroNode(SDValue Elt) {
|
|
return ((isa<ConstantSDNode>(Elt) &&
|
|
cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
|
|
(isa<ConstantFPSDNode>(Elt) &&
|
|
cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
|
|
}
|
|
|
|
/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
|
|
/// to an zero vector.
|
|
/// FIXME: move to dag combiner / method on ShuffleVectorSDNode
|
|
static bool isZeroShuffle(ShuffleVectorSDNode *N) {
|
|
SDValue V1 = N->getOperand(0);
|
|
SDValue V2 = N->getOperand(1);
|
|
unsigned NumElems = N->getValueType(0).getVectorNumElements();
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
int Idx = N->getMaskElt(i);
|
|
if (Idx >= (int)NumElems) {
|
|
unsigned Opc = V2.getOpcode();
|
|
if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
|
|
continue;
|
|
if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V2.getOperand(Idx-NumElems)))
|
|
return false;
|
|
} else if (Idx >= 0) {
|
|
unsigned Opc = V1.getOpcode();
|
|
if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
|
|
continue;
|
|
if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V1.getOperand(Idx)))
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/// getZeroVector - Returns a vector of specified type with all zero elements.
|
|
///
|
|
static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
|
|
DebugLoc dl) {
|
|
assert(VT.isVector() && "Expected a vector type");
|
|
|
|
// Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
|
|
// type. This ensures they get CSE'd.
|
|
SDValue Vec;
|
|
if (VT.getSizeInBits() == 64) { // MMX
|
|
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
|
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
|
|
} else if (HasSSE2) { // SSE2
|
|
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
|
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
|
|
} else { // SSE1
|
|
SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
|
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
|
|
}
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
|
|
}
|
|
|
|
/// getOnesVector - Returns a vector of specified type with all bits set.
|
|
///
|
|
static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
|
|
assert(VT.isVector() && "Expected a vector type");
|
|
|
|
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
|
|
// type. This ensures they get CSE'd.
|
|
SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
|
|
SDValue Vec;
|
|
if (VT.getSizeInBits() == 64) // MMX
|
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
|
|
else // SSE
|
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
|
|
}
|
|
|
|
|
|
/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
|
|
/// that point to V2 points to its first element.
|
|
static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
|
|
MVT VT = SVOp->getValueType(0);
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
|
|
bool Changed = false;
|
|
SmallVector<int, 8> MaskVec;
|
|
SVOp->getMask(MaskVec);
|
|
|
|
for (unsigned i = 0; i != NumElems; ++i) {
|
|
if (MaskVec[i] > (int)NumElems) {
|
|
MaskVec[i] = NumElems;
|
|
Changed = true;
|
|
}
|
|
}
|
|
if (Changed)
|
|
return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
|
|
SVOp->getOperand(1), &MaskVec[0]);
|
|
return SDValue(SVOp, 0);
|
|
}
|
|
|
|
/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
|
|
/// operation of specified width.
|
|
static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
|
|
SDValue V2) {
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
SmallVector<int, 8> Mask;
|
|
Mask.push_back(NumElems);
|
|
for (unsigned i = 1; i != NumElems; ++i)
|
|
Mask.push_back(i);
|
|
return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
|
|
}
|
|
|
|
/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
|
|
static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
|
|
SDValue V2) {
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
SmallVector<int, 8> Mask;
|
|
for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
|
|
Mask.push_back(i);
|
|
Mask.push_back(i + NumElems);
|
|
}
|
|
return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
|
|
}
|
|
|
|
/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
|
|
static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
|
|
SDValue V2) {
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
unsigned Half = NumElems/2;
|
|
SmallVector<int, 8> Mask;
|
|
for (unsigned i = 0; i != Half; ++i) {
|
|
Mask.push_back(i + Half);
|
|
Mask.push_back(i + NumElems + Half);
|
|
}
|
|
return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
|
|
}
|
|
|
|
/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
|
|
static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
|
|
bool HasSSE2) {
|
|
if (SV->getValueType(0).getVectorNumElements() <= 4)
|
|
return SDValue(SV, 0);
|
|
|
|
MVT PVT = MVT::v4f32;
|
|
MVT VT = SV->getValueType(0);
|
|
DebugLoc dl = SV->getDebugLoc();
|
|
SDValue V1 = SV->getOperand(0);
|
|
int NumElems = VT.getVectorNumElements();
|
|
int EltNo = SV->getSplatIndex();
|
|
|
|
// unpack elements to the correct location
|
|
while (NumElems > 4) {
|
|
if (EltNo < NumElems/2) {
|
|
V1 = getUnpackl(DAG, dl, VT, V1, V1);
|
|
} else {
|
|
V1 = getUnpackh(DAG, dl, VT, V1, V1);
|
|
EltNo -= NumElems/2;
|
|
}
|
|
NumElems >>= 1;
|
|
}
|
|
|
|
// Perform the splat.
|
|
int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
|
|
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
|
|
V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
|
|
}
|
|
|
|
/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
|
|
/// vector of zero or undef vector. This produces a shuffle where the low
|
|
/// element of V2 is swizzled into the zero/undef vector, landing at element
|
|
/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
|
|
static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
|
|
bool isZero, bool HasSSE2,
|
|
SelectionDAG &DAG) {
|
|
MVT VT = V2.getValueType();
|
|
SDValue V1 = isZero
|
|
? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
SmallVector<int, 16> MaskVec;
|
|
for (unsigned i = 0; i != NumElems; ++i)
|
|
// If this is the insertion idx, put the low elt of V2 here.
|
|
MaskVec.push_back(i == Idx ? NumElems : i);
|
|
return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
|
|
}
|
|
|
|
/// getNumOfConsecutiveZeros - Return the number of elements in a result of
|
|
/// a shuffle that is zero.
|
|
static
|
|
unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
|
|
bool Low, SelectionDAG &DAG) {
|
|
unsigned NumZeros = 0;
|
|
for (int i = 0; i < NumElems; ++i) {
|
|
unsigned Index = Low ? i : NumElems-i-1;
|
|
int Idx = SVOp->getMaskElt(Index);
|
|
if (Idx < 0) {
|
|
++NumZeros;
|
|
continue;
|
|
}
|
|
SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
|
|
if (Elt.getNode() && isZeroNode(Elt))
|
|
++NumZeros;
|
|
else
|
|
break;
|
|
}
|
|
return NumZeros;
|
|
}
|
|
|
|
/// isVectorShift - Returns true if the shuffle can be implemented as a
|
|
/// logical left or right shift of a vector.
|
|
/// FIXME: split into pslldqi, psrldqi, palignr variants.
|
|
static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
|
|
bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
|
|
int NumElems = SVOp->getValueType(0).getVectorNumElements();
|
|
|
|
isLeft = true;
|
|
unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
|
|
if (!NumZeros) {
|
|
isLeft = false;
|
|
NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
|
|
if (!NumZeros)
|
|
return false;
|
|
}
|
|
bool SeenV1 = false;
|
|
bool SeenV2 = false;
|
|
for (int i = NumZeros; i < NumElems; ++i) {
|
|
int Val = isLeft ? (i - NumZeros) : i;
|
|
int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
|
|
if (Idx < 0)
|
|
continue;
|
|
if (Idx < NumElems)
|
|
SeenV1 = true;
|
|
else {
|
|
Idx -= NumElems;
|
|
SeenV2 = true;
|
|
}
|
|
if (Idx != Val)
|
|
return false;
|
|
}
|
|
if (SeenV1 && SeenV2)
|
|
return false;
|
|
|
|
ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
|
|
ShAmt = NumZeros;
|
|
return true;
|
|
}
|
|
|
|
|
|
/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
|
|
///
|
|
static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
|
|
unsigned NumNonZero, unsigned NumZero,
|
|
SelectionDAG &DAG, TargetLowering &TLI) {
|
|
if (NumNonZero > 8)
|
|
return SDValue();
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue V(0, 0);
|
|
bool First = true;
|
|
for (unsigned i = 0; i < 16; ++i) {
|
|
bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
|
|
if (ThisIsNonZero && First) {
|
|
if (NumZero)
|
|
V = getZeroVector(MVT::v8i16, true, DAG, dl);
|
|
else
|
|
V = DAG.getUNDEF(MVT::v8i16);
|
|
First = false;
|
|
}
|
|
|
|
if ((i & 1) != 0) {
|
|
SDValue ThisElt(0, 0), LastElt(0, 0);
|
|
bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
|
|
if (LastIsNonZero) {
|
|
LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
|
|
MVT::i16, Op.getOperand(i-1));
|
|
}
|
|
if (ThisIsNonZero) {
|
|
ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
|
|
ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
|
|
ThisElt, DAG.getConstant(8, MVT::i8));
|
|
if (LastIsNonZero)
|
|
ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
|
|
} else
|
|
ThisElt = LastElt;
|
|
|
|
if (ThisElt.getNode())
|
|
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
|
|
DAG.getIntPtrConstant(i/2));
|
|
}
|
|
}
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
|
|
}
|
|
|
|
/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
|
|
///
|
|
static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
|
|
unsigned NumNonZero, unsigned NumZero,
|
|
SelectionDAG &DAG, TargetLowering &TLI) {
|
|
if (NumNonZero > 4)
|
|
return SDValue();
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue V(0, 0);
|
|
bool First = true;
|
|
for (unsigned i = 0; i < 8; ++i) {
|
|
bool isNonZero = (NonZeros & (1 << i)) != 0;
|
|
if (isNonZero) {
|
|
if (First) {
|
|
if (NumZero)
|
|
V = getZeroVector(MVT::v8i16, true, DAG, dl);
|
|
else
|
|
V = DAG.getUNDEF(MVT::v8i16);
|
|
First = false;
|
|
}
|
|
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
|
|
MVT::v8i16, V, Op.getOperand(i),
|
|
DAG.getIntPtrConstant(i));
|
|
}
|
|
}
|
|
|
|
return V;
|
|
}
|
|
|
|
/// getVShift - Return a vector logical shift node.
|
|
///
|
|
static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
|
|
unsigned NumBits, SelectionDAG &DAG,
|
|
const TargetLowering &TLI, DebugLoc dl) {
|
|
bool isMMX = VT.getSizeInBits() == 64;
|
|
MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
|
|
unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
|
|
SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
|
|
DAG.getNode(Opc, dl, ShVT, SrcOp,
|
|
DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
// All zero's are handled with pxor, all one's are handled with pcmpeqd.
|
|
if (ISD::isBuildVectorAllZeros(Op.getNode())
|
|
|| ISD::isBuildVectorAllOnes(Op.getNode())) {
|
|
// Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
|
|
// 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
|
|
// eliminated on x86-32 hosts.
|
|
if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
|
|
return Op;
|
|
|
|
if (ISD::isBuildVectorAllOnes(Op.getNode()))
|
|
return getOnesVector(Op.getValueType(), DAG, dl);
|
|
return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
|
|
}
|
|
|
|
MVT VT = Op.getValueType();
|
|
MVT EVT = VT.getVectorElementType();
|
|
unsigned EVTBits = EVT.getSizeInBits();
|
|
|
|
unsigned NumElems = Op.getNumOperands();
|
|
unsigned NumZero = 0;
|
|
unsigned NumNonZero = 0;
|
|
unsigned NonZeros = 0;
|
|
bool IsAllConstants = true;
|
|
SmallSet<SDValue, 8> Values;
|
|
for (unsigned i = 0; i < NumElems; ++i) {
|
|
SDValue Elt = Op.getOperand(i);
|
|
if (Elt.getOpcode() == ISD::UNDEF)
|
|
continue;
|
|
Values.insert(Elt);
|
|
if (Elt.getOpcode() != ISD::Constant &&
|
|
Elt.getOpcode() != ISD::ConstantFP)
|
|
IsAllConstants = false;
|
|
if (isZeroNode(Elt))
|
|
NumZero++;
|
|
else {
|
|
NonZeros |= (1 << i);
|
|
NumNonZero++;
|
|
}
|
|
}
|
|
|
|
if (NumNonZero == 0) {
|
|
// All undef vector. Return an UNDEF. All zero vectors were handled above.
|
|
return DAG.getUNDEF(VT);
|
|
}
|
|
|
|
// Special case for single non-zero, non-undef, element.
|
|
if (NumNonZero == 1) {
|
|
unsigned Idx = CountTrailingZeros_32(NonZeros);
|
|
SDValue Item = Op.getOperand(Idx);
|
|
|
|
// If this is an insertion of an i64 value on x86-32, and if the top bits of
|
|
// the value are obviously zero, truncate the value to i32 and do the
|
|
// insertion that way. Only do this if the value is non-constant or if the
|
|
// value is a constant being inserted into element 0. It is cheaper to do
|
|
// a constant pool load than it is to do a movd + shuffle.
|
|
if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
|
|
(!IsAllConstants || Idx == 0)) {
|
|
if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
|
|
// Handle MMX and SSE both.
|
|
MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
|
|
unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
|
|
|
|
// Truncate the value (which may itself be a constant) to i32, and
|
|
// convert it to a vector with movd (S2V+shuffle to zero extend).
|
|
Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
|
|
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
|
|
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
|
|
Subtarget->hasSSE2(), DAG);
|
|
|
|
// Now we have our 32-bit value zero extended in the low element of
|
|
// a vector. If Idx != 0, swizzle it into place.
|
|
if (Idx != 0) {
|
|
SmallVector<int, 4> Mask;
|
|
Mask.push_back(Idx);
|
|
for (unsigned i = 1; i != VecElts; ++i)
|
|
Mask.push_back(i);
|
|
Item = DAG.getVectorShuffle(VecVT, dl, Item,
|
|
DAG.getUNDEF(Item.getValueType()),
|
|
&Mask[0]);
|
|
}
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
|
|
}
|
|
}
|
|
|
|
// If we have a constant or non-constant insertion into the low element of
|
|
// a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
|
|
// the rest of the elements. This will be matched as movd/movq/movss/movsd
|
|
// depending on what the source datatype is.
|
|
if (Idx == 0) {
|
|
if (NumZero == 0) {
|
|
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
|
|
} else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 ||
|
|
(EVT == MVT::i64 && Subtarget->is64Bit())) {
|
|
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
|
|
// Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
|
|
return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
|
|
DAG);
|
|
} else if (EVT == MVT::i16 || EVT == MVT::i8) {
|
|
Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
|
|
MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
|
|
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
|
|
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
|
|
Subtarget->hasSSE2(), DAG);
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
|
|
}
|
|
}
|
|
|
|
// Is it a vector logical left shift?
|
|
if (NumElems == 2 && Idx == 1 &&
|
|
isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
|
|
unsigned NumBits = VT.getSizeInBits();
|
|
return getVShift(true, VT,
|
|
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
|
|
VT, Op.getOperand(1)),
|
|
NumBits/2, DAG, *this, dl);
|
|
}
|
|
|
|
if (IsAllConstants) // Otherwise, it's better to do a constpool load.
|
|
return SDValue();
|
|
|
|
// Otherwise, if this is a vector with i32 or f32 elements, and the element
|
|
// is a non-constant being inserted into an element other than the low one,
|
|
// we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
|
|
// movd/movss) to move this into the low element, then shuffle it into
|
|
// place.
|
|
if (EVTBits == 32) {
|
|
Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
|
|
|
|
// Turn it into a shuffle of zero and zero-extended scalar to vector.
|
|
Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
|
|
Subtarget->hasSSE2(), DAG);
|
|
SmallVector<int, 8> MaskVec;
|
|
for (unsigned i = 0; i < NumElems; i++)
|
|
MaskVec.push_back(i == Idx ? 0 : 1);
|
|
return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
|
|
}
|
|
}
|
|
|
|
// Splat is obviously ok. Let legalizer expand it to a shuffle.
|
|
if (Values.size() == 1)
|
|
return SDValue();
|
|
|
|
// A vector full of immediates; various special cases are already
|
|
// handled, so this is best done with a single constant-pool load.
|
|
if (IsAllConstants)
|
|
return SDValue();
|
|
|
|
// Let legalizer expand 2-wide build_vectors.
|
|
if (EVTBits == 64) {
|
|
if (NumNonZero == 1) {
|
|
// One half is zero or undef.
|
|
unsigned Idx = CountTrailingZeros_32(NonZeros);
|
|
SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
|
|
Op.getOperand(Idx));
|
|
return getShuffleVectorZeroOrUndef(V2, Idx, true,
|
|
Subtarget->hasSSE2(), DAG);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
// If element VT is < 32 bits, convert it to inserts into a zero vector.
|
|
if (EVTBits == 8 && NumElems == 16) {
|
|
SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
|
|
*this);
|
|
if (V.getNode()) return V;
|
|
}
|
|
|
|
if (EVTBits == 16 && NumElems == 8) {
|
|
SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
|
|
*this);
|
|
if (V.getNode()) return V;
|
|
}
|
|
|
|
// If element VT is == 32 bits, turn it into a number of shuffles.
|
|
SmallVector<SDValue, 8> V;
|
|
V.resize(NumElems);
|
|
if (NumElems == 4 && NumZero > 0) {
|
|
for (unsigned i = 0; i < 4; ++i) {
|
|
bool isZero = !(NonZeros & (1 << i));
|
|
if (isZero)
|
|
V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
|
|
else
|
|
V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
|
|
}
|
|
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
|
|
default: break;
|
|
case 0:
|
|
V[i] = V[i*2]; // Must be a zero vector.
|
|
break;
|
|
case 1:
|
|
V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
|
|
break;
|
|
case 2:
|
|
V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
|
|
break;
|
|
case 3:
|
|
V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
|
|
break;
|
|
}
|
|
}
|
|
|
|
SmallVector<int, 8> MaskVec;
|
|
bool Reverse = (NonZeros & 0x3) == 2;
|
|
for (unsigned i = 0; i < 2; ++i)
|
|
MaskVec.push_back(Reverse ? 1-i : i);
|
|
Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
|
|
for (unsigned i = 0; i < 2; ++i)
|
|
MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
|
|
return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
|
|
}
|
|
|
|
if (Values.size() > 2) {
|
|
// If we have SSE 4.1, Expand into a number of inserts unless the number of
|
|
// values to be inserted is equal to the number of elements, in which case
|
|
// use the unpack code below in the hopes of matching the consecutive elts
|
|
// load merge pattern for shuffles.
|
|
// FIXME: We could probably just check that here directly.
|
|
if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
|
|
getSubtarget()->hasSSE41()) {
|
|
V[0] = DAG.getUNDEF(VT);
|
|
for (unsigned i = 0; i < NumElems; ++i)
|
|
if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
|
|
V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
|
|
Op.getOperand(i), DAG.getIntPtrConstant(i));
|
|
return V[0];
|
|
}
|
|
// Expand into a number of unpckl*.
|
|
// e.g. for v4f32
|
|
// Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
|
|
// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
|
|
// Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
|
|
for (unsigned i = 0; i < NumElems; ++i)
|
|
V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
|
|
NumElems >>= 1;
|
|
while (NumElems != 0) {
|
|
for (unsigned i = 0; i < NumElems; ++i)
|
|
V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
|
|
NumElems >>= 1;
|
|
}
|
|
return V[0];
|
|
}
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
// v8i16 shuffles - Prefer shuffles in the following order:
|
|
// 1. [all] pshuflw, pshufhw, optional move
|
|
// 2. [ssse3] 1 x pshufb
|
|
// 3. [ssse3] 2 x pshufb + 1 x por
|
|
// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
|
|
static
|
|
SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
|
|
SelectionDAG &DAG, X86TargetLowering &TLI) {
|
|
SDValue V1 = SVOp->getOperand(0);
|
|
SDValue V2 = SVOp->getOperand(1);
|
|
DebugLoc dl = SVOp->getDebugLoc();
|
|
SmallVector<int, 8> MaskVals;
|
|
|
|
// Determine if more than 1 of the words in each of the low and high quadwords
|
|
// of the result come from the same quadword of one of the two inputs. Undef
|
|
// mask values count as coming from any quadword, for better codegen.
|
|
SmallVector<unsigned, 4> LoQuad(4);
|
|
SmallVector<unsigned, 4> HiQuad(4);
|
|
BitVector InputQuads(4);
|
|
for (unsigned i = 0; i < 8; ++i) {
|
|
SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
|
|
int EltIdx = SVOp->getMaskElt(i);
|
|
MaskVals.push_back(EltIdx);
|
|
if (EltIdx < 0) {
|
|
++Quad[0];
|
|
++Quad[1];
|
|
++Quad[2];
|
|
++Quad[3];
|
|
continue;
|
|
}
|
|
++Quad[EltIdx / 4];
|
|
InputQuads.set(EltIdx / 4);
|
|
}
|
|
|
|
int BestLoQuad = -1;
|
|
unsigned MaxQuad = 1;
|
|
for (unsigned i = 0; i < 4; ++i) {
|
|
if (LoQuad[i] > MaxQuad) {
|
|
BestLoQuad = i;
|
|
MaxQuad = LoQuad[i];
|
|
}
|
|
}
|
|
|
|
int BestHiQuad = -1;
|
|
MaxQuad = 1;
|
|
for (unsigned i = 0; i < 4; ++i) {
|
|
if (HiQuad[i] > MaxQuad) {
|
|
BestHiQuad = i;
|
|
MaxQuad = HiQuad[i];
|
|
}
|
|
}
|
|
|
|
// For SSSE3, If all 8 words of the result come from only 1 quadword of each
|
|
// of the two input vectors, shuffle them into one input vector so only a
|
|
// single pshufb instruction is necessary. If There are more than 2 input
|
|
// quads, disable the next transformation since it does not help SSSE3.
|
|
bool V1Used = InputQuads[0] || InputQuads[1];
|
|
bool V2Used = InputQuads[2] || InputQuads[3];
|
|
if (TLI.getSubtarget()->hasSSSE3()) {
|
|
if (InputQuads.count() == 2 && V1Used && V2Used) {
|
|
BestLoQuad = InputQuads.find_first();
|
|
BestHiQuad = InputQuads.find_next(BestLoQuad);
|
|
}
|
|
if (InputQuads.count() > 2) {
|
|
BestLoQuad = -1;
|
|
BestHiQuad = -1;
|
|
}
|
|
}
|
|
|
|
// If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
|
|
// the shuffle mask. If a quad is scored as -1, that means that it contains
|
|
// words from all 4 input quadwords.
|
|
SDValue NewV;
|
|
if (BestLoQuad >= 0 || BestHiQuad >= 0) {
|
|
SmallVector<int, 8> MaskV;
|
|
MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
|
|
MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
|
|
NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
|
|
NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
|
|
|
|
// Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
|
|
// source words for the shuffle, to aid later transformations.
|
|
bool AllWordsInNewV = true;
|
|
bool InOrder[2] = { true, true };
|
|
for (unsigned i = 0; i != 8; ++i) {
|
|
int idx = MaskVals[i];
|
|
if (idx != (int)i)
|
|
InOrder[i/4] = false;
|
|
if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
|
|
continue;
|
|
AllWordsInNewV = false;
|
|
break;
|
|
}
|
|
|
|
bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
|
|
if (AllWordsInNewV) {
|
|
for (int i = 0; i != 8; ++i) {
|
|
int idx = MaskVals[i];
|
|
if (idx < 0)
|
|
continue;
|
|
idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
|
|
if ((idx != i) && idx < 4)
|
|
pshufhw = false;
|
|
if ((idx != i) && idx > 3)
|
|
pshuflw = false;
|
|
}
|
|
V1 = NewV;
|
|
V2Used = false;
|
|
BestLoQuad = 0;
|
|
BestHiQuad = 1;
|
|
}
|
|
|
|
// If we've eliminated the use of V2, and the new mask is a pshuflw or
|
|
// pshufhw, that's as cheap as it gets. Return the new shuffle.
|
|
if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
|
|
return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
|
|
DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
|
|
}
|
|
}
|
|
|
|
// If we have SSSE3, and all words of the result are from 1 input vector,
|
|
// case 2 is generated, otherwise case 3 is generated. If no SSSE3
|
|
// is present, fall back to case 4.
|
|
if (TLI.getSubtarget()->hasSSSE3()) {
|
|
SmallVector<SDValue,16> pshufbMask;
|
|
|
|
// If we have elements from both input vectors, set the high bit of the
|
|
// shuffle mask element to zero out elements that come from V2 in the V1
|
|
// mask, and elements that come from V1 in the V2 mask, so that the two
|
|
// results can be OR'd together.
|
|
bool TwoInputs = V1Used && V2Used;
|
|
for (unsigned i = 0; i != 8; ++i) {
|
|
int EltIdx = MaskVals[i] * 2;
|
|
if (TwoInputs && (EltIdx >= 16)) {
|
|
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
|
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
|
continue;
|
|
}
|
|
pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
|
|
pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
|
|
}
|
|
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
|
|
V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
|
|
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
|
MVT::v16i8, &pshufbMask[0], 16));
|
|
if (!TwoInputs)
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
|
|
|
|
// Calculate the shuffle mask for the second input, shuffle it, and
|
|
// OR it with the first shuffled input.
|
|
pshufbMask.clear();
|
|
for (unsigned i = 0; i != 8; ++i) {
|
|
int EltIdx = MaskVals[i] * 2;
|
|
if (EltIdx < 16) {
|
|
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
|
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
|
continue;
|
|
}
|
|
pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
|
|
pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
|
|
}
|
|
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
|
|
V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
|
|
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
|
MVT::v16i8, &pshufbMask[0], 16));
|
|
V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
|
|
}
|
|
|
|
// If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
|
|
// and update MaskVals with new element order.
|
|
BitVector InOrder(8);
|
|
if (BestLoQuad >= 0) {
|
|
SmallVector<int, 8> MaskV;
|
|
for (int i = 0; i != 4; ++i) {
|
|
int idx = MaskVals[i];
|
|
if (idx < 0) {
|
|
MaskV.push_back(-1);
|
|
InOrder.set(i);
|
|
} else if ((idx / 4) == BestLoQuad) {
|
|
MaskV.push_back(idx & 3);
|
|
InOrder.set(i);
|
|
} else {
|
|
MaskV.push_back(-1);
|
|
}
|
|
}
|
|
for (unsigned i = 4; i != 8; ++i)
|
|
MaskV.push_back(i);
|
|
NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
|
|
&MaskV[0]);
|
|
}
|
|
|
|
// If BestHi >= 0, generate a pshufhw to put the high elements in order,
|
|
// and update MaskVals with the new element order.
|
|
if (BestHiQuad >= 0) {
|
|
SmallVector<int, 8> MaskV;
|
|
for (unsigned i = 0; i != 4; ++i)
|
|
MaskV.push_back(i);
|
|
for (unsigned i = 4; i != 8; ++i) {
|
|
int idx = MaskVals[i];
|
|
if (idx < 0) {
|
|
MaskV.push_back(-1);
|
|
InOrder.set(i);
|
|
} else if ((idx / 4) == BestHiQuad) {
|
|
MaskV.push_back((idx & 3) + 4);
|
|
InOrder.set(i);
|
|
} else {
|
|
MaskV.push_back(-1);
|
|
}
|
|
}
|
|
NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
|
|
&MaskV[0]);
|
|
}
|
|
|
|
// In case BestHi & BestLo were both -1, which means each quadword has a word
|
|
// from each of the four input quadwords, calculate the InOrder bitvector now
|
|
// before falling through to the insert/extract cleanup.
|
|
if (BestLoQuad == -1 && BestHiQuad == -1) {
|
|
NewV = V1;
|
|
for (int i = 0; i != 8; ++i)
|
|
if (MaskVals[i] < 0 || MaskVals[i] == i)
|
|
InOrder.set(i);
|
|
}
|
|
|
|
// The other elements are put in the right place using pextrw and pinsrw.
|
|
for (unsigned i = 0; i != 8; ++i) {
|
|
if (InOrder[i])
|
|
continue;
|
|
int EltIdx = MaskVals[i];
|
|
if (EltIdx < 0)
|
|
continue;
|
|
SDValue ExtOp = (EltIdx < 8)
|
|
? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
|
|
DAG.getIntPtrConstant(EltIdx))
|
|
: DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
|
|
DAG.getIntPtrConstant(EltIdx - 8));
|
|
NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
|
|
DAG.getIntPtrConstant(i));
|
|
}
|
|
return NewV;
|
|
}
|
|
|
|
// v16i8 shuffles - Prefer shuffles in the following order:
|
|
// 1. [ssse3] 1 x pshufb
|
|
// 2. [ssse3] 2 x pshufb + 1 x por
|
|
// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
|
|
static
|
|
SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
|
|
SelectionDAG &DAG, X86TargetLowering &TLI) {
|
|
SDValue V1 = SVOp->getOperand(0);
|
|
SDValue V2 = SVOp->getOperand(1);
|
|
DebugLoc dl = SVOp->getDebugLoc();
|
|
SmallVector<int, 16> MaskVals;
|
|
SVOp->getMask(MaskVals);
|
|
|
|
// If we have SSSE3, case 1 is generated when all result bytes come from
|
|
// one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
|
|
// present, fall back to case 3.
|
|
// FIXME: kill V2Only once shuffles are canonizalized by getNode.
|
|
bool V1Only = true;
|
|
bool V2Only = true;
|
|
for (unsigned i = 0; i < 16; ++i) {
|
|
int EltIdx = MaskVals[i];
|
|
if (EltIdx < 0)
|
|
continue;
|
|
if (EltIdx < 16)
|
|
V2Only = false;
|
|
else
|
|
V1Only = false;
|
|
}
|
|
|
|
// If SSSE3, use 1 pshufb instruction per vector with elements in the result.
|
|
if (TLI.getSubtarget()->hasSSSE3()) {
|
|
SmallVector<SDValue,16> pshufbMask;
|
|
|
|
// If all result elements are from one input vector, then only translate
|
|
// undef mask values to 0x80 (zero out result) in the pshufb mask.
|
|
//
|
|
// Otherwise, we have elements from both input vectors, and must zero out
|
|
// elements that come from V2 in the first mask, and V1 in the second mask
|
|
// so that we can OR them together.
|
|
bool TwoInputs = !(V1Only || V2Only);
|
|
for (unsigned i = 0; i != 16; ++i) {
|
|
int EltIdx = MaskVals[i];
|
|
if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
|
|
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
|
continue;
|
|
}
|
|
pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
|
|
}
|
|
// If all the elements are from V2, assign it to V1 and return after
|
|
// building the first pshufb.
|
|
if (V2Only)
|
|
V1 = V2;
|
|
V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
|
|
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
|
MVT::v16i8, &pshufbMask[0], 16));
|
|
if (!TwoInputs)
|
|
return V1;
|
|
|
|
// Calculate the shuffle mask for the second input, shuffle it, and
|
|
// OR it with the first shuffled input.
|
|
pshufbMask.clear();
|
|
for (unsigned i = 0; i != 16; ++i) {
|
|
int EltIdx = MaskVals[i];
|
|
if (EltIdx < 16) {
|
|
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
|
continue;
|
|
}
|
|
pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
|
|
}
|
|
V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
|
|
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
|
MVT::v16i8, &pshufbMask[0], 16));
|
|
return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
|
|
}
|
|
|
|
// No SSSE3 - Calculate in place words and then fix all out of place words
|
|
// With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
|
|
// the 16 different words that comprise the two doublequadword input vectors.
|
|
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
|
|
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
|
|
SDValue NewV = V2Only ? V2 : V1;
|
|
for (int i = 0; i != 8; ++i) {
|
|
int Elt0 = MaskVals[i*2];
|
|
int Elt1 = MaskVals[i*2+1];
|
|
|
|
// This word of the result is all undef, skip it.
|
|
if (Elt0 < 0 && Elt1 < 0)
|
|
continue;
|
|
|
|
// This word of the result is already in the correct place, skip it.
|
|
if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
|
|
continue;
|
|
if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
|
|
continue;
|
|
|
|
SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
|
|
SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
|
|
SDValue InsElt;
|
|
|
|
// If Elt0 and Elt1 are defined, are consecutive, and can be load
|
|
// using a single extract together, load it and store it.
|
|
if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
|
|
InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
|
|
DAG.getIntPtrConstant(Elt1 / 2));
|
|
NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
|
|
DAG.getIntPtrConstant(i));
|
|
continue;
|
|
}
|
|
|
|
// If Elt1 is defined, extract it from the appropriate source. If the
|
|
// source byte is not also odd, shift the extracted word left 8 bits
|
|
// otherwise clear the bottom 8 bits if we need to do an or.
|
|
if (Elt1 >= 0) {
|
|
InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
|
|
DAG.getIntPtrConstant(Elt1 / 2));
|
|
if ((Elt1 & 1) == 0)
|
|
InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
|
|
DAG.getConstant(8, TLI.getShiftAmountTy()));
|
|
else if (Elt0 >= 0)
|
|
InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
|
|
DAG.getConstant(0xFF00, MVT::i16));
|
|
}
|
|
// If Elt0 is defined, extract it from the appropriate source. If the
|
|
// source byte is not also even, shift the extracted word right 8 bits. If
|
|
// Elt1 was also defined, OR the extracted values together before
|
|
// inserting them in the result.
|
|
if (Elt0 >= 0) {
|
|
SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
|
|
Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
|
|
if ((Elt0 & 1) != 0)
|
|
InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
|
|
DAG.getConstant(8, TLI.getShiftAmountTy()));
|
|
else if (Elt1 >= 0)
|
|
InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
|
|
DAG.getConstant(0x00FF, MVT::i16));
|
|
InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
|
|
: InsElt0;
|
|
}
|
|
NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
|
|
DAG.getIntPtrConstant(i));
|
|
}
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
|
|
}
|
|
|
|
/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
|
|
/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
|
|
/// done when every pair / quad of shuffle mask elements point to elements in
|
|
/// the right sequence. e.g.
|
|
/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
|
|
static
|
|
SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
|
|
SelectionDAG &DAG,
|
|
TargetLowering &TLI, DebugLoc dl) {
|
|
MVT VT = SVOp->getValueType(0);
|
|
SDValue V1 = SVOp->getOperand(0);
|
|
SDValue V2 = SVOp->getOperand(1);
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
unsigned NewWidth = (NumElems == 4) ? 2 : 4;
|
|
MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
|
|
MVT MaskEltVT = MaskVT.getVectorElementType();
|
|
MVT NewVT = MaskVT;
|
|
switch (VT.getSimpleVT()) {
|
|
default: assert(false && "Unexpected!");
|
|
case MVT::v4f32: NewVT = MVT::v2f64; break;
|
|
case MVT::v4i32: NewVT = MVT::v2i64; break;
|
|
case MVT::v8i16: NewVT = MVT::v4i32; break;
|
|
case MVT::v16i8: NewVT = MVT::v4i32; break;
|
|
}
|
|
|
|
if (NewWidth == 2) {
|
|
if (VT.isInteger())
|
|
NewVT = MVT::v2i64;
|
|
else
|
|
NewVT = MVT::v2f64;
|
|
}
|
|
int Scale = NumElems / NewWidth;
|
|
SmallVector<int, 8> MaskVec;
|
|
for (unsigned i = 0; i < NumElems; i += Scale) {
|
|
int StartIdx = -1;
|
|
for (int j = 0; j < Scale; ++j) {
|
|
int EltIdx = SVOp->getMaskElt(i+j);
|
|
if (EltIdx < 0)
|
|
continue;
|
|
if (StartIdx == -1)
|
|
StartIdx = EltIdx - (EltIdx % Scale);
|
|
if (EltIdx != StartIdx + j)
|
|
return SDValue();
|
|
}
|
|
if (StartIdx == -1)
|
|
MaskVec.push_back(-1);
|
|
else
|
|
MaskVec.push_back(StartIdx / Scale);
|
|
}
|
|
|
|
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
|
|
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
|
|
return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
|
|
}
|
|
|
|
/// getVZextMovL - Return a zero-extending vector move low node.
|
|
///
|
|
static SDValue getVZextMovL(MVT VT, MVT OpVT,
|
|
SDValue SrcOp, SelectionDAG &DAG,
|
|
const X86Subtarget *Subtarget, DebugLoc dl) {
|
|
if (VT == MVT::v2f64 || VT == MVT::v4f32) {
|
|
LoadSDNode *LD = NULL;
|
|
if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
|
|
LD = dyn_cast<LoadSDNode>(SrcOp);
|
|
if (!LD) {
|
|
// movssrr and movsdrr do not clear top bits. Try to use movd, movq
|
|
// instead.
|
|
MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
|
|
if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
|
|
SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
|
|
SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
|
|
SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
|
|
// PR2108
|
|
OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
|
|
DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
|
|
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
|
|
OpVT,
|
|
SrcOp.getOperand(0)
|
|
.getOperand(0))));
|
|
}
|
|
}
|
|
}
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
|
|
DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl,
|
|
OpVT, SrcOp)));
|
|
}
|
|
|
|
/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
|
|
/// shuffles.
|
|
static SDValue
|
|
LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
|
|
SDValue V1 = SVOp->getOperand(0);
|
|
SDValue V2 = SVOp->getOperand(1);
|
|
DebugLoc dl = SVOp->getDebugLoc();
|
|
MVT VT = SVOp->getValueType(0);
|
|
|
|
SmallVector<std::pair<int, int>, 8> Locs;
|
|
Locs.resize(4);
|
|
SmallVector<int, 8> Mask1(4U, -1);
|
|
SmallVector<int, 8> PermMask;
|
|
SVOp->getMask(PermMask);
|
|
|
|
unsigned NumHi = 0;
|
|
unsigned NumLo = 0;
|
|
for (unsigned i = 0; i != 4; ++i) {
|
|
int Idx = PermMask[i];
|
|
if (Idx < 0) {
|
|
Locs[i] = std::make_pair(-1, -1);
|
|
} else {
|
|
assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
|
|
if (Idx < 4) {
|
|
Locs[i] = std::make_pair(0, NumLo);
|
|
Mask1[NumLo] = Idx;
|
|
NumLo++;
|
|
} else {
|
|
Locs[i] = std::make_pair(1, NumHi);
|
|
if (2+NumHi < 4)
|
|
Mask1[2+NumHi] = Idx;
|
|
NumHi++;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (NumLo <= 2 && NumHi <= 2) {
|
|
// If no more than two elements come from either vector. This can be
|
|
// implemented with two shuffles. First shuffle gather the elements.
|
|
// The second shuffle, which takes the first shuffle as both of its
|
|
// vector operands, put the elements into the right order.
|
|
V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
|
|
|
|
SmallVector<int, 8> Mask2(4U, -1);
|
|
|
|
for (unsigned i = 0; i != 4; ++i) {
|
|
if (Locs[i].first == -1)
|
|
continue;
|
|
else {
|
|
unsigned Idx = (i < 2) ? 0 : 4;
|
|
Idx += Locs[i].first * 2 + Locs[i].second;
|
|
Mask2[i] = Idx;
|
|
}
|
|
}
|
|
|
|
return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
|
|
} else if (NumLo == 3 || NumHi == 3) {
|
|
// Otherwise, we must have three elements from one vector, call it X, and
|
|
// one element from the other, call it Y. First, use a shufps to build an
|
|
// intermediate vector with the one element from Y and the element from X
|
|
// that will be in the same half in the final destination (the indexes don't
|
|
// matter). Then, use a shufps to build the final vector, taking the half
|
|
// containing the element from Y from the intermediate, and the other half
|
|
// from X.
|
|
if (NumHi == 3) {
|
|
// Normalize it so the 3 elements come from V1.
|
|
CommuteVectorShuffleMask(PermMask, VT);
|
|
std::swap(V1, V2);
|
|
}
|
|
|
|
// Find the element from V2.
|
|
unsigned HiIndex;
|
|
for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
|
|
int Val = PermMask[HiIndex];
|
|
if (Val < 0)
|
|
continue;
|
|
if (Val >= 4)
|
|
break;
|
|
}
|
|
|
|
Mask1[0] = PermMask[HiIndex];
|
|
Mask1[1] = -1;
|
|
Mask1[2] = PermMask[HiIndex^1];
|
|
Mask1[3] = -1;
|
|
V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
|
|
|
|
if (HiIndex >= 2) {
|
|
Mask1[0] = PermMask[0];
|
|
Mask1[1] = PermMask[1];
|
|
Mask1[2] = HiIndex & 1 ? 6 : 4;
|
|
Mask1[3] = HiIndex & 1 ? 4 : 6;
|
|
return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
|
|
} else {
|
|
Mask1[0] = HiIndex & 1 ? 2 : 0;
|
|
Mask1[1] = HiIndex & 1 ? 0 : 2;
|
|
Mask1[2] = PermMask[2];
|
|
Mask1[3] = PermMask[3];
|
|
if (Mask1[2] >= 0)
|
|
Mask1[2] += 4;
|
|
if (Mask1[3] >= 0)
|
|
Mask1[3] += 4;
|
|
return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
|
|
}
|
|
}
|
|
|
|
// Break it into (shuffle shuffle_hi, shuffle_lo).
|
|
Locs.clear();
|
|
SmallVector<int,8> LoMask(4U, -1);
|
|
SmallVector<int,8> HiMask(4U, -1);
|
|
|
|
SmallVector<int,8> *MaskPtr = &LoMask;
|
|
unsigned MaskIdx = 0;
|
|
unsigned LoIdx = 0;
|
|
unsigned HiIdx = 2;
|
|
for (unsigned i = 0; i != 4; ++i) {
|
|
if (i == 2) {
|
|
MaskPtr = &HiMask;
|
|
MaskIdx = 1;
|
|
LoIdx = 0;
|
|
HiIdx = 2;
|
|
}
|
|
int Idx = PermMask[i];
|
|
if (Idx < 0) {
|
|
Locs[i] = std::make_pair(-1, -1);
|
|
} else if (Idx < 4) {
|
|
Locs[i] = std::make_pair(MaskIdx, LoIdx);
|
|
(*MaskPtr)[LoIdx] = Idx;
|
|
LoIdx++;
|
|
} else {
|
|
Locs[i] = std::make_pair(MaskIdx, HiIdx);
|
|
(*MaskPtr)[HiIdx] = Idx;
|
|
HiIdx++;
|
|
}
|
|
}
|
|
|
|
SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
|
|
SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
|
|
SmallVector<int, 8> MaskOps;
|
|
for (unsigned i = 0; i != 4; ++i) {
|
|
if (Locs[i].first == -1) {
|
|
MaskOps.push_back(-1);
|
|
} else {
|
|
unsigned Idx = Locs[i].first * 4 + Locs[i].second;
|
|
MaskOps.push_back(Idx);
|
|
}
|
|
}
|
|
return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
|
|
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
|
|
SDValue V1 = Op.getOperand(0);
|
|
SDValue V2 = Op.getOperand(1);
|
|
MVT VT = Op.getValueType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
bool isMMX = VT.getSizeInBits() == 64;
|
|
bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
|
|
bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
|
|
bool V1IsSplat = false;
|
|
bool V2IsSplat = false;
|
|
|
|
if (isZeroShuffle(SVOp))
|
|
return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
|
|
|
|
// Promote splats to v4f32.
|
|
if (SVOp->isSplat()) {
|
|
if (isMMX || NumElems < 4)
|
|
return Op;
|
|
return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
|
|
}
|
|
|
|
// If the shuffle can be profitably rewritten as a narrower shuffle, then
|
|
// do it!
|
|
if (VT == MVT::v8i16 || VT == MVT::v16i8) {
|
|
SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
|
|
if (NewOp.getNode())
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
|
|
LowerVECTOR_SHUFFLE(NewOp, DAG));
|
|
} else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
|
|
// FIXME: Figure out a cleaner way to do this.
|
|
// Try to make use of movq to zero out the top part.
|
|
if (ISD::isBuildVectorAllZeros(V2.getNode())) {
|
|
SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
|
|
if (NewOp.getNode()) {
|
|
if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
|
|
return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
|
|
DAG, Subtarget, dl);
|
|
}
|
|
} else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
|
|
SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
|
|
if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
|
|
return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
|
|
DAG, Subtarget, dl);
|
|
}
|
|
}
|
|
|
|
if (X86::isPSHUFDMask(SVOp))
|
|
return Op;
|
|
|
|
// Check if this can be converted into a logical shift.
|
|
bool isLeft = false;
|
|
unsigned ShAmt = 0;
|
|
SDValue ShVal;
|
|
bool isShift = getSubtarget()->hasSSE2() &&
|
|
isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
|
|
if (isShift && ShVal.hasOneUse()) {
|
|
// If the shifted value has multiple uses, it may be cheaper to use
|
|
// v_set0 + movlhps or movhlps, etc.
|
|
MVT EVT = VT.getVectorElementType();
|
|
ShAmt *= EVT.getSizeInBits();
|
|
return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
|
|
}
|
|
|
|
if (X86::isMOVLMask(SVOp)) {
|
|
if (V1IsUndef)
|
|
return V2;
|
|
if (ISD::isBuildVectorAllZeros(V1.getNode()))
|
|
return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
|
|
if (!isMMX)
|
|
return Op;
|
|
}
|
|
|
|
// FIXME: fold these into legal mask.
|
|
if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
|
|
X86::isMOVSLDUPMask(SVOp) ||
|
|
X86::isMOVHLPSMask(SVOp) ||
|
|
X86::isMOVHPMask(SVOp) ||
|
|
X86::isMOVLPMask(SVOp)))
|
|
return Op;
|
|
|
|
if (ShouldXformToMOVHLPS(SVOp) ||
|
|
ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
|
|
return CommuteVectorShuffle(SVOp, DAG);
|
|
|
|
if (isShift) {
|
|
// No better options. Use a vshl / vsrl.
|
|
MVT EVT = VT.getVectorElementType();
|
|
ShAmt *= EVT.getSizeInBits();
|
|
return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
|
|
}
|
|
|
|
bool Commuted = false;
|
|
// FIXME: This should also accept a bitcast of a splat? Be careful, not
|
|
// 1,1,1,1 -> v8i16 though.
|
|
V1IsSplat = isSplatVector(V1.getNode());
|
|
V2IsSplat = isSplatVector(V2.getNode());
|
|
|
|
// Canonicalize the splat or undef, if present, to be on the RHS.
|
|
if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
|
|
Op = CommuteVectorShuffle(SVOp, DAG);
|
|
SVOp = cast<ShuffleVectorSDNode>(Op);
|
|
V1 = SVOp->getOperand(0);
|
|
V2 = SVOp->getOperand(1);
|
|
std::swap(V1IsSplat, V2IsSplat);
|
|
std::swap(V1IsUndef, V2IsUndef);
|
|
Commuted = true;
|
|
}
|
|
|
|
if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
|
|
// Shuffling low element of v1 into undef, just return v1.
|
|
if (V2IsUndef)
|
|
return V1;
|
|
// If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
|
|
// the instruction selector will not match, so get a canonical MOVL with
|
|
// swapped operands to undo the commute.
|
|
return getMOVL(DAG, dl, VT, V2, V1);
|
|
}
|
|
|
|
if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
|
|
X86::isUNPCKH_v_undef_Mask(SVOp) ||
|
|
X86::isUNPCKLMask(SVOp) ||
|
|
X86::isUNPCKHMask(SVOp))
|
|
return Op;
|
|
|
|
if (V2IsSplat) {
|
|
// Normalize mask so all entries that point to V2 points to its first
|
|
// element then try to match unpck{h|l} again. If match, return a
|
|
// new vector_shuffle with the corrected mask.
|
|
SDValue NewMask = NormalizeMask(SVOp, DAG);
|
|
ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
|
|
if (NSVOp != SVOp) {
|
|
if (X86::isUNPCKLMask(NSVOp, true)) {
|
|
return NewMask;
|
|
} else if (X86::isUNPCKHMask(NSVOp, true)) {
|
|
return NewMask;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (Commuted) {
|
|
// Commute is back and try unpck* again.
|
|
// FIXME: this seems wrong.
|
|
SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
|
|
ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
|
|
if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
|
|
X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
|
|
X86::isUNPCKLMask(NewSVOp) ||
|
|
X86::isUNPCKHMask(NewSVOp))
|
|
return NewOp;
|
|
}
|
|
|
|
// FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
|
|
|
|
// Normalize the node to match x86 shuffle ops if needed
|
|
if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
|
|
return CommuteVectorShuffle(SVOp, DAG);
|
|
|
|
// Check for legal shuffle and return?
|
|
SmallVector<int, 16> PermMask;
|
|
SVOp->getMask(PermMask);
|
|
if (isShuffleMaskLegal(PermMask, VT))
|
|
return Op;
|
|
|
|
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
|
|
if (VT == MVT::v8i16) {
|
|
SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
|
|
if (NewOp.getNode())
|
|
return NewOp;
|
|
}
|
|
|
|
if (VT == MVT::v16i8) {
|
|
SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
|
|
if (NewOp.getNode())
|
|
return NewOp;
|
|
}
|
|
|
|
// Handle all 4 wide cases with a number of shuffles except for MMX.
|
|
if (NumElems == 4 && !isMMX)
|
|
return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
MVT VT = Op.getValueType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
if (VT.getSizeInBits() == 8) {
|
|
SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
|
|
DAG.getValueType(VT));
|
|
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
|
|
} else if (VT.getSizeInBits() == 16) {
|
|
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
|
// If Idx is 0, it's cheaper to do a move instead of a pextrw.
|
|
if (Idx == 0)
|
|
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
|
|
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl,
|
|
MVT::v4i32,
|
|
Op.getOperand(0)),
|
|
Op.getOperand(1)));
|
|
SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
|
|
DAG.getValueType(VT));
|
|
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
|
|
} else if (VT == MVT::f32) {
|
|
// EXTRACTPS outputs to a GPR32 register which will require a movd to copy
|
|
// the result back to FR32 register. It's only worth matching if the
|
|
// result has a single use which is a store or a bitcast to i32. And in
|
|
// the case of a store, it's not worth it if the index is a constant 0,
|
|
// because a MOVSSmr can be used instead, which is smaller and faster.
|
|
if (!Op.hasOneUse())
|
|
return SDValue();
|
|
SDNode *User = *Op.getNode()->use_begin();
|
|
if ((User->getOpcode() != ISD::STORE ||
|
|
(isa<ConstantSDNode>(Op.getOperand(1)) &&
|
|
cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
|
|
(User->getOpcode() != ISD::BIT_CONVERT ||
|
|
User->getValueType(0) != MVT::i32))
|
|
return SDValue();
|
|
SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
|
|
Op.getOperand(0)),
|
|
Op.getOperand(1));
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
|
|
} else if (VT == MVT::i32) {
|
|
// ExtractPS works with constant index.
|
|
if (isa<ConstantSDNode>(Op.getOperand(1)))
|
|
return Op;
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
|
|
if (!isa<ConstantSDNode>(Op.getOperand(1)))
|
|
return SDValue();
|
|
|
|
if (Subtarget->hasSSE41()) {
|
|
SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
|
|
if (Res.getNode())
|
|
return Res;
|
|
}
|
|
|
|
MVT VT = Op.getValueType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
// TODO: handle v16i8.
|
|
if (VT.getSizeInBits() == 16) {
|
|
SDValue Vec = Op.getOperand(0);
|
|
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
|
if (Idx == 0)
|
|
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
|
|
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl,
|
|
MVT::v4i32, Vec),
|
|
Op.getOperand(1)));
|
|
// Transform it so it match pextrw which produces a 32-bit result.
|
|
MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
|
|
SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
|
|
DAG.getValueType(VT));
|
|
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
|
|
} else if (VT.getSizeInBits() == 32) {
|
|
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
|
if (Idx == 0)
|
|
return Op;
|
|
|
|
// SHUFPS the element to the lowest double word, then movss.
|
|
int Mask[4] = { Idx, -1, -1, -1 };
|
|
MVT VVT = Op.getOperand(0).getValueType();
|
|
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
|
|
DAG.getUNDEF(VVT), Mask);
|
|
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
|
|
DAG.getIntPtrConstant(0));
|
|
} else if (VT.getSizeInBits() == 64) {
|
|
// FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
|
|
// FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
|
|
// to match extract_elt for f64.
|
|
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
|
if (Idx == 0)
|
|
return Op;
|
|
|
|
// UNPCKHPD the element to the lowest double word, then movsd.
|
|
// Note if the lower 64 bits of the result of the UNPCKHPD is then stored
|
|
// to a f64mem, the whole operation is folded into a single MOVHPDmr.
|
|
int Mask[2] = { 1, -1 };
|
|
MVT VVT = Op.getOperand(0).getValueType();
|
|
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
|
|
DAG.getUNDEF(VVT), Mask);
|
|
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
|
|
DAG.getIntPtrConstant(0));
|
|
}
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
|
|
MVT VT = Op.getValueType();
|
|
MVT EVT = VT.getVectorElementType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue N0 = Op.getOperand(0);
|
|
SDValue N1 = Op.getOperand(1);
|
|
SDValue N2 = Op.getOperand(2);
|
|
|
|
if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
|
|
isa<ConstantSDNode>(N2)) {
|
|
unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
|
|
: X86ISD::PINSRW;
|
|
// Transform it so it match pinsr{b,w} which expects a GR32 as its second
|
|
// argument.
|
|
if (N1.getValueType() != MVT::i32)
|
|
N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
|
|
if (N2.getValueType() != MVT::i32)
|
|
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
|
|
return DAG.getNode(Opc, dl, VT, N0, N1, N2);
|
|
} else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
|
|
// Bits [7:6] of the constant are the source select. This will always be
|
|
// zero here. The DAG Combiner may combine an extract_elt index into these
|
|
// bits. For example (insert (extract, 3), 2) could be matched by putting
|
|
// the '3' into bits [7:6] of X86ISD::INSERTPS.
|
|
// Bits [5:4] of the constant are the destination select. This is the
|
|
// value of the incoming immediate.
|
|
// Bits [3:0] of the constant are the zero mask. The DAG Combiner may
|
|
// combine either bitwise AND or insert of float 0.0 to set these bits.
|
|
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
|
|
return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
|
|
} else if (EVT == MVT::i32) {
|
|
// InsertPS works with constant index.
|
|
if (isa<ConstantSDNode>(N2))
|
|
return Op;
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
|
|
MVT VT = Op.getValueType();
|
|
MVT EVT = VT.getVectorElementType();
|
|
|
|
if (Subtarget->hasSSE41())
|
|
return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
|
|
|
|
if (EVT == MVT::i8)
|
|
return SDValue();
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue N0 = Op.getOperand(0);
|
|
SDValue N1 = Op.getOperand(1);
|
|
SDValue N2 = Op.getOperand(2);
|
|
|
|
if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
|
|
// Transform it so it match pinsrw which expects a 16-bit value in a GR32
|
|
// as its second argument.
|
|
if (N1.getValueType() != MVT::i32)
|
|
N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
|
|
if (N2.getValueType() != MVT::i32)
|
|
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
|
|
return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
if (Op.getValueType() == MVT::v2f32)
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
|
|
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
|
|
Op.getOperand(0))));
|
|
|
|
SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
|
|
MVT VT = MVT::v2i32;
|
|
switch (Op.getValueType().getSimpleVT()) {
|
|
default: break;
|
|
case MVT::v16i8:
|
|
case MVT::v8i16:
|
|
VT = MVT::v4i32;
|
|
break;
|
|
}
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
|
|
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
|
|
}
|
|
|
|
// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
|
|
// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
|
|
// one of the above mentioned nodes. It has to be wrapped because otherwise
|
|
// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
|
|
// be used to form addressing mode. These wrapped nodes will be selected
|
|
// into MOV32ri.
|
|
SDValue
|
|
X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
|
|
// FIXME there isn't really any debug info here, should come from the parent
|
|
DebugLoc dl = CP->getDebugLoc();
|
|
SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
|
|
CP->getAlignment());
|
|
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
|
|
// With PIC, the address is actually $g + Offset.
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
|
|
!Subtarget->isPICStyleRIPRel()) {
|
|
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
DAG.getNode(X86ISD::GlobalBaseReg,
|
|
DebugLoc::getUnknownLoc(),
|
|
getPointerTy()),
|
|
Result);
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
|
|
int64_t Offset,
|
|
SelectionDAG &DAG) const {
|
|
bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
|
|
bool ExtraLoadRequired =
|
|
Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
|
|
|
|
// Create the TargetGlobalAddress node, folding in the constant
|
|
// offset if it is legal.
|
|
SDValue Result;
|
|
if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
|
|
Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
|
|
Offset = 0;
|
|
} else
|
|
Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
|
|
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
|
|
|
|
// With PIC, the address is actually $g + Offset.
|
|
if (IsPic && !Subtarget->isPICStyleRIPRel()) {
|
|
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
|
|
Result);
|
|
}
|
|
|
|
// For Darwin & Mingw32, external and weak symbols are indirect, so we want to
|
|
// load the value at address GV, not the value of GV itself. This means that
|
|
// the GlobalAddress must be in the base or index register of the address, not
|
|
// the GV offset field. Platform check is inside GVRequiresExtraLoad() call
|
|
// The same applies for external symbols during PIC codegen
|
|
if (ExtraLoadRequired)
|
|
Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
|
|
PseudoSourceValue::getGOT(), 0);
|
|
|
|
// If there was a non-zero offset that we didn't fold, create an explicit
|
|
// addition for it.
|
|
if (Offset != 0)
|
|
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
|
|
DAG.getConstant(Offset, getPointerTy()));
|
|
|
|
return Result;
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
|
|
return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
|
|
}
|
|
|
|
static SDValue
|
|
GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
|
|
SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg) {
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
DebugLoc dl = GA->getDebugLoc();
|
|
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
|
|
GA->getValueType(0),
|
|
GA->getOffset());
|
|
if (InFlag) {
|
|
SDValue Ops[] = { Chain, TGA, *InFlag };
|
|
Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
|
|
} else {
|
|
SDValue Ops[] = { Chain, TGA };
|
|
Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
|
|
}
|
|
SDValue Flag = Chain.getValue(1);
|
|
return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
|
|
}
|
|
|
|
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
|
|
static SDValue
|
|
LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
|
|
const MVT PtrVT) {
|
|
SDValue InFlag;
|
|
DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
|
|
SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
|
|
DAG.getNode(X86ISD::GlobalBaseReg,
|
|
DebugLoc::getUnknownLoc(),
|
|
PtrVT), InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX);
|
|
}
|
|
|
|
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
|
|
static SDValue
|
|
LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
|
|
const MVT PtrVT) {
|
|
return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX);
|
|
}
|
|
|
|
// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
|
|
// "local exec" model.
|
|
static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
|
|
const MVT PtrVT, TLSModel::Model model,
|
|
bool is64Bit) {
|
|
DebugLoc dl = GA->getDebugLoc();
|
|
// Get the Thread Pointer
|
|
SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
|
|
DebugLoc::getUnknownLoc(), PtrVT,
|
|
DAG.getRegister(is64Bit? X86::FS : X86::GS,
|
|
MVT::i32));
|
|
|
|
SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
|
|
NULL, 0);
|
|
|
|
// emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
|
|
// exec)
|
|
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
|
|
GA->getValueType(0),
|
|
GA->getOffset());
|
|
SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
|
|
|
|
if (model == TLSModel::InitialExec)
|
|
Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
|
|
PseudoSourceValue::getGOT(), 0);
|
|
|
|
// The address of the thread local variable is the add of the thread
|
|
// pointer with the offset of the variable.
|
|
return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
|
|
// TODO: implement the "local dynamic" model
|
|
// TODO: implement the "initial exec"model for pic executables
|
|
assert(Subtarget->isTargetELF() &&
|
|
"TLS not implemented for non-ELF targets");
|
|
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
|
|
GlobalValue *GV = GA->getGlobal();
|
|
TLSModel::Model model =
|
|
getTLSModel (GV, getTargetMachine().getRelocationModel());
|
|
if (Subtarget->is64Bit()) {
|
|
switch (model) {
|
|
case TLSModel::GeneralDynamic:
|
|
case TLSModel::LocalDynamic: // not implemented
|
|
return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
|
|
|
|
case TLSModel::InitialExec:
|
|
case TLSModel::LocalExec:
|
|
return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, true);
|
|
}
|
|
} else {
|
|
switch (model) {
|
|
case TLSModel::GeneralDynamic:
|
|
case TLSModel::LocalDynamic: // not implemented
|
|
return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
|
|
|
|
case TLSModel::InitialExec:
|
|
case TLSModel::LocalExec:
|
|
return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, false);
|
|
}
|
|
}
|
|
assert(0 && "Unreachable");
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
|
|
// FIXME there isn't really any debug info here
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
|
|
SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
|
|
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
|
|
// With PIC, the address is actually $g + Offset.
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
|
|
!Subtarget->isPICStyleRIPRel()) {
|
|
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
DAG.getNode(X86ISD::GlobalBaseReg,
|
|
DebugLoc::getUnknownLoc(),
|
|
getPointerTy()),
|
|
Result);
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
|
// FIXME there isn't really any debug into here
|
|
DebugLoc dl = JT->getDebugLoc();
|
|
SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
|
|
Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
|
|
// With PIC, the address is actually $g + Offset.
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
|
|
!Subtarget->isPICStyleRIPRel()) {
|
|
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
DAG.getNode(X86ISD::GlobalBaseReg,
|
|
DebugLoc::getUnknownLoc(),
|
|
getPointerTy()),
|
|
Result);
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
|
|
/// take a 2 x i32 value to shift plus a shift amount.
|
|
SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
|
|
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
|
|
MVT VT = Op.getValueType();
|
|
unsigned VTBits = VT.getSizeInBits();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
|
|
SDValue ShOpLo = Op.getOperand(0);
|
|
SDValue ShOpHi = Op.getOperand(1);
|
|
SDValue ShAmt = Op.getOperand(2);
|
|
SDValue Tmp1 = isSRA ?
|
|
DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
|
|
DAG.getConstant(VTBits - 1, MVT::i8)) :
|
|
DAG.getConstant(0, VT);
|
|
|
|
SDValue Tmp2, Tmp3;
|
|
if (Op.getOpcode() == ISD::SHL_PARTS) {
|
|
Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
|
|
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
|
|
} else {
|
|
Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
|
|
Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
|
|
}
|
|
|
|
SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
|
|
DAG.getConstant(VTBits, MVT::i8));
|
|
SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
|
|
AndNode, DAG.getConstant(0, MVT::i8));
|
|
|
|
SDValue Hi, Lo;
|
|
SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
|
|
SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
|
|
SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
|
|
|
|
if (Op.getOpcode() == ISD::SHL_PARTS) {
|
|
Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
|
|
Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
|
|
} else {
|
|
Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
|
|
Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
|
|
}
|
|
|
|
SDValue Ops[2] = { Lo, Hi };
|
|
return DAG.getMergeValues(Ops, 2, dl);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
|
|
MVT SrcVT = Op.getOperand(0).getValueType();
|
|
|
|
if (SrcVT.isVector()) {
|
|
if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
|
|
return Op;
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
|
|
"Unknown SINT_TO_FP to lower!");
|
|
|
|
// These are really Legal; return the operand so the caller accepts it as
|
|
// Legal.
|
|
if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
|
|
return Op;
|
|
if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
|
|
Subtarget->is64Bit()) {
|
|
return Op;
|
|
}
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
unsigned Size = SrcVT.getSizeInBits()/8;
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
|
|
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
|
|
StackSlot,
|
|
PseudoSourceValue::getFixedStack(SSFI), 0);
|
|
return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
|
|
}
|
|
|
|
SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
|
|
SDValue StackSlot,
|
|
SelectionDAG &DAG) {
|
|
// Build the FILD
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDVTList Tys;
|
|
bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
|
|
if (useSSE)
|
|
Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
|
|
else
|
|
Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(StackSlot);
|
|
Ops.push_back(DAG.getValueType(SrcVT));
|
|
SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
|
|
Tys, &Ops[0], Ops.size());
|
|
|
|
if (useSSE) {
|
|
Chain = Result.getValue(1);
|
|
SDValue InFlag = Result.getValue(2);
|
|
|
|
// FIXME: Currently the FST is flagged to the FILD_FLAG. This
|
|
// shouldn't be necessary except that RFP cannot be live across
|
|
// multiple blocks. When stackifier is fixed, they can be uncoupled.
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
|
|
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
Tys = DAG.getVTList(MVT::Other);
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(Result);
|
|
Ops.push_back(StackSlot);
|
|
Ops.push_back(DAG.getValueType(Op.getValueType()));
|
|
Ops.push_back(InFlag);
|
|
Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
|
|
Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
|
|
PseudoSourceValue::getFixedStack(SSFI), 0);
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
|
|
SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
|
|
// This algorithm is not obvious. Here it is in C code, more or less:
|
|
/*
|
|
double uint64_to_double( uint32_t hi, uint32_t lo ) {
|
|
static const __m128i exp = { 0x4330000045300000ULL, 0 };
|
|
static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
|
|
|
|
// Copy ints to xmm registers.
|
|
__m128i xh = _mm_cvtsi32_si128( hi );
|
|
__m128i xl = _mm_cvtsi32_si128( lo );
|
|
|
|
// Combine into low half of a single xmm register.
|
|
__m128i x = _mm_unpacklo_epi32( xh, xl );
|
|
__m128d d;
|
|
double sd;
|
|
|
|
// Merge in appropriate exponents to give the integer bits the right
|
|
// magnitude.
|
|
x = _mm_unpacklo_epi32( x, exp );
|
|
|
|
// Subtract away the biases to deal with the IEEE-754 double precision
|
|
// implicit 1.
|
|
d = _mm_sub_pd( (__m128d) x, bias );
|
|
|
|
// All conversions up to here are exact. The correctly rounded result is
|
|
// calculated using the current rounding mode using the following
|
|
// horizontal add.
|
|
d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
|
|
_mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
|
|
// store doesn't really need to be here (except
|
|
// maybe to zero the other double)
|
|
return sd;
|
|
}
|
|
*/
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
// Build some magic constants.
|
|
std::vector<Constant*> CV0;
|
|
CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
|
|
CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
|
|
CV0.push_back(ConstantInt::get(APInt(32, 0)));
|
|
CV0.push_back(ConstantInt::get(APInt(32, 0)));
|
|
Constant *C0 = ConstantVector::get(CV0);
|
|
SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
|
|
|
|
std::vector<Constant*> CV1;
|
|
CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
|
|
CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
|
|
Constant *C1 = ConstantVector::get(CV1);
|
|
SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
|
|
|
|
SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
|
|
DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
|
|
Op.getOperand(0),
|
|
DAG.getIntPtrConstant(1)));
|
|
SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
|
|
DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
|
|
Op.getOperand(0),
|
|
DAG.getIntPtrConstant(0)));
|
|
SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
|
|
SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
|
|
PseudoSourceValue::getConstantPool(), 0,
|
|
false, 16);
|
|
SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
|
|
SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
|
|
SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
|
|
PseudoSourceValue::getConstantPool(), 0,
|
|
false, 16);
|
|
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
|
|
|
|
// Add the halves; easiest way is to swap them into another reg first.
|
|
int ShufMask[2] = { 1, -1 };
|
|
SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
|
|
DAG.getUNDEF(MVT::v2f64), ShufMask);
|
|
SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
|
|
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
|
|
DAG.getIntPtrConstant(0));
|
|
}
|
|
|
|
// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
|
|
SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
// FP constant to bias correct the final result.
|
|
SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
|
|
MVT::f64);
|
|
|
|
// Load the 32-bit value into an XMM register.
|
|
SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
|
|
DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
|
|
Op.getOperand(0),
|
|
DAG.getIntPtrConstant(0)));
|
|
|
|
Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
|
|
DAG.getIntPtrConstant(0));
|
|
|
|
// Or the load with the bias.
|
|
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
|
|
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
|
|
MVT::v2f64, Load)),
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
|
|
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
|
|
MVT::v2f64, Bias)));
|
|
Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
|
|
DAG.getIntPtrConstant(0));
|
|
|
|
// Subtract the bias.
|
|
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
|
|
|
|
// Handle final rounding.
|
|
MVT DestVT = Op.getValueType();
|
|
|
|
if (DestVT.bitsLT(MVT::f64)) {
|
|
return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
|
|
DAG.getIntPtrConstant(0));
|
|
} else if (DestVT.bitsGT(MVT::f64)) {
|
|
return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
|
|
}
|
|
|
|
// Handle final rounding.
|
|
return Sub;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue N0 = Op.getOperand(0);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
// Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
|
|
// optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
|
|
// the optimization here.
|
|
if (DAG.SignBitIsZero(N0))
|
|
return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
|
|
|
|
MVT SrcVT = N0.getValueType();
|
|
if (SrcVT == MVT::i64) {
|
|
// We only handle SSE2 f64 target here; caller can expand the rest.
|
|
if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
|
|
return SDValue();
|
|
|
|
return LowerUINT_TO_FP_i64(Op, DAG);
|
|
} else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
|
|
return LowerUINT_TO_FP_i32(Op, DAG);
|
|
}
|
|
|
|
assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
|
|
|
|
// Make a 64-bit buffer, and use it to build an FILD.
|
|
SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
|
|
SDValue WordOff = DAG.getConstant(4, getPointerTy());
|
|
SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
|
|
getPointerTy(), StackSlot, WordOff);
|
|
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
|
|
StackSlot, NULL, 0);
|
|
SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
|
|
OffsetSlot, NULL, 0);
|
|
return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
|
|
}
|
|
|
|
std::pair<SDValue,SDValue> X86TargetLowering::
|
|
FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
MVT DstTy = Op.getValueType();
|
|
|
|
if (!IsSigned) {
|
|
assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
|
|
DstTy = MVT::i64;
|
|
}
|
|
|
|
assert(DstTy.getSimpleVT() <= MVT::i64 &&
|
|
DstTy.getSimpleVT() >= MVT::i16 &&
|
|
"Unknown FP_TO_SINT to lower!");
|
|
|
|
// These are really Legal.
|
|
if (DstTy == MVT::i32 &&
|
|
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
|
|
return std::make_pair(SDValue(), SDValue());
|
|
if (Subtarget->is64Bit() &&
|
|
DstTy == MVT::i64 &&
|
|
isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
|
|
return std::make_pair(SDValue(), SDValue());
|
|
|
|
// We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
|
|
// stack slot.
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
unsigned MemSize = DstTy.getSizeInBits()/8;
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
|
|
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
unsigned Opc;
|
|
switch (DstTy.getSimpleVT()) {
|
|
default: assert(0 && "Invalid FP_TO_SINT to lower!");
|
|
case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
|
|
case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
|
|
case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
|
|
}
|
|
|
|
SDValue Chain = DAG.getEntryNode();
|
|
SDValue Value = Op.getOperand(0);
|
|
if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
|
|
assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
|
|
Chain = DAG.getStore(Chain, dl, Value, StackSlot,
|
|
PseudoSourceValue::getFixedStack(SSFI), 0);
|
|
SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
|
|
SDValue Ops[] = {
|
|
Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
|
|
};
|
|
Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
|
|
Chain = Value.getValue(1);
|
|
SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
|
|
StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
}
|
|
|
|
// Build the FP_TO_INT*_IN_MEM
|
|
SDValue Ops[] = { Chain, Value, StackSlot };
|
|
SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
|
|
|
|
return std::make_pair(FIST, StackSlot);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
|
|
if (Op.getValueType().isVector()) {
|
|
if (Op.getValueType() == MVT::v2i32 &&
|
|
Op.getOperand(0).getValueType() == MVT::v2f64) {
|
|
return Op;
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
|
|
SDValue FIST = Vals.first, StackSlot = Vals.second;
|
|
// If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
|
|
if (FIST.getNode() == 0) return Op;
|
|
|
|
// Load the result.
|
|
return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
|
|
FIST, StackSlot, NULL, 0);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
|
|
std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
|
|
SDValue FIST = Vals.first, StackSlot = Vals.second;
|
|
assert(FIST.getNode() && "Unexpected failure");
|
|
|
|
// Load the result.
|
|
return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
|
|
FIST, StackSlot, NULL, 0);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
MVT VT = Op.getValueType();
|
|
MVT EltVT = VT;
|
|
if (VT.isVector())
|
|
EltVT = VT.getVectorElementType();
|
|
std::vector<Constant*> CV;
|
|
if (EltVT == MVT::f64) {
|
|
Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
} else {
|
|
Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
}
|
|
Constant *C = ConstantVector::get(CV);
|
|
SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
|
|
SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
|
|
PseudoSourceValue::getConstantPool(), 0,
|
|
false, 16);
|
|
return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
MVT VT = Op.getValueType();
|
|
MVT EltVT = VT;
|
|
unsigned EltNum = 1;
|
|
if (VT.isVector()) {
|
|
EltVT = VT.getVectorElementType();
|
|
EltNum = VT.getVectorNumElements();
|
|
}
|
|
std::vector<Constant*> CV;
|
|
if (EltVT == MVT::f64) {
|
|
Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
} else {
|
|
Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
CV.push_back(C);
|
|
}
|
|
Constant *C = ConstantVector::get(CV);
|
|
SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
|
|
SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
|
|
PseudoSourceValue::getConstantPool(), 0,
|
|
false, 16);
|
|
if (VT.isVector()) {
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
|
|
DAG.getNode(ISD::XOR, dl, MVT::v2i64,
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
|
|
Op.getOperand(0)),
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
|
|
} else {
|
|
return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
|
|
}
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue Op0 = Op.getOperand(0);
|
|
SDValue Op1 = Op.getOperand(1);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
MVT VT = Op.getValueType();
|
|
MVT SrcVT = Op1.getValueType();
|
|
|
|
// If second operand is smaller, extend it first.
|
|
if (SrcVT.bitsLT(VT)) {
|
|
Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
|
|
SrcVT = VT;
|
|
}
|
|
// And if it is bigger, shrink it first.
|
|
if (SrcVT.bitsGT(VT)) {
|
|
Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
|
|
SrcVT = VT;
|
|
}
|
|
|
|
// At this point the operands and the result should have the same
|
|
// type, and that won't be f80 since that is not custom lowered.
|
|
|
|
// First get the sign bit of second operand.
|
|
std::vector<Constant*> CV;
|
|
if (SrcVT == MVT::f64) {
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
|
|
} else {
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
|
|
}
|
|
Constant *C = ConstantVector::get(CV);
|
|
SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
|
|
SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
|
|
PseudoSourceValue::getConstantPool(), 0,
|
|
false, 16);
|
|
SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
|
|
|
|
// Shift sign bit right or left if the two operands have different types.
|
|
if (SrcVT.bitsGT(VT)) {
|
|
// Op0 is MVT::f32, Op1 is MVT::f64.
|
|
SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
|
|
SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
|
|
DAG.getConstant(32, MVT::i32));
|
|
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
|
|
SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
|
|
DAG.getIntPtrConstant(0));
|
|
}
|
|
|
|
// Clear first operand sign bit.
|
|
CV.clear();
|
|
if (VT == MVT::f64) {
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
|
|
} else {
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
|
|
CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
|
|
}
|
|
C = ConstantVector::get(CV);
|
|
CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
|
|
SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
|
|
PseudoSourceValue::getConstantPool(), 0,
|
|
false, 16);
|
|
SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
|
|
|
|
// Or the value with the sign bit.
|
|
return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
|
|
}
|
|
|
|
/// Emit nodes that will be selected as "test Op0,Op0", or something
|
|
/// equivalent.
|
|
SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
|
|
SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
// CF and OF aren't always set the way we want. Determine which
|
|
// of these we need.
|
|
bool NeedCF = false;
|
|
bool NeedOF = false;
|
|
switch (X86CC) {
|
|
case X86::COND_A: case X86::COND_AE:
|
|
case X86::COND_B: case X86::COND_BE:
|
|
NeedCF = true;
|
|
break;
|
|
case X86::COND_G: case X86::COND_GE:
|
|
case X86::COND_L: case X86::COND_LE:
|
|
case X86::COND_O: case X86::COND_NO:
|
|
NeedOF = true;
|
|
break;
|
|
default: break;
|
|
}
|
|
|
|
// See if we can use the EFLAGS value from the operand instead of
|
|
// doing a separate TEST. TEST always sets OF and CF to 0, so unless
|
|
// we prove that the arithmetic won't overflow, we can't use OF or CF.
|
|
if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
|
|
unsigned Opcode = 0;
|
|
unsigned NumOperands = 0;
|
|
switch (Op.getNode()->getOpcode()) {
|
|
case ISD::ADD:
|
|
// Due to an isel shortcoming, be conservative if this add is likely to
|
|
// be selected as part of a load-modify-store instruction. When the root
|
|
// node in a match is a store, isel doesn't know how to remap non-chain
|
|
// non-flag uses of other nodes in the match, such as the ADD in this
|
|
// case. This leads to the ADD being left around and reselected, with
|
|
// the result being two adds in the output.
|
|
for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
|
|
UE = Op.getNode()->use_end(); UI != UE; ++UI)
|
|
if (UI->getOpcode() == ISD::STORE)
|
|
goto default_case;
|
|
if (ConstantSDNode *C =
|
|
dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
|
|
// An add of one will be selected as an INC.
|
|
if (C->getAPIntValue() == 1) {
|
|
Opcode = X86ISD::INC;
|
|
NumOperands = 1;
|
|
break;
|
|
}
|
|
// An add of negative one (subtract of one) will be selected as a DEC.
|
|
if (C->getAPIntValue().isAllOnesValue()) {
|
|
Opcode = X86ISD::DEC;
|
|
NumOperands = 1;
|
|
break;
|
|
}
|
|
}
|
|
// Otherwise use a regular EFLAGS-setting add.
|
|
Opcode = X86ISD::ADD;
|
|
NumOperands = 2;
|
|
break;
|
|
case ISD::SUB:
|
|
// Due to the ISEL shortcoming noted above, be conservative if this sub is
|
|
// likely to be selected as part of a load-modify-store instruction.
|
|
for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
|
|
UE = Op.getNode()->use_end(); UI != UE; ++UI)
|
|
if (UI->getOpcode() == ISD::STORE)
|
|
goto default_case;
|
|
// Otherwise use a regular EFLAGS-setting sub.
|
|
Opcode = X86ISD::SUB;
|
|
NumOperands = 2;
|
|
break;
|
|
case X86ISD::ADD:
|
|
case X86ISD::SUB:
|
|
case X86ISD::INC:
|
|
case X86ISD::DEC:
|
|
return SDValue(Op.getNode(), 1);
|
|
default:
|
|
default_case:
|
|
break;
|
|
}
|
|
if (Opcode != 0) {
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
|
|
SmallVector<SDValue, 4> Ops;
|
|
for (unsigned i = 0; i != NumOperands; ++i)
|
|
Ops.push_back(Op.getOperand(i));
|
|
SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
|
|
DAG.ReplaceAllUsesWith(Op, New);
|
|
return SDValue(New.getNode(), 1);
|
|
}
|
|
}
|
|
|
|
// Otherwise just emit a CMP with 0, which is the TEST pattern.
|
|
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
|
|
DAG.getConstant(0, Op.getValueType()));
|
|
}
|
|
|
|
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
|
|
/// equivalent.
|
|
SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
|
|
SelectionDAG &DAG) {
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
|
|
if (C->getAPIntValue() == 0)
|
|
return EmitTest(Op0, X86CC, DAG);
|
|
|
|
DebugLoc dl = Op0.getDebugLoc();
|
|
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
|
|
assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
|
|
SDValue Op0 = Op.getOperand(0);
|
|
SDValue Op1 = Op.getOperand(1);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
|
|
|
|
// Lower (X & (1 << N)) == 0 to BT(X, N).
|
|
// Lower ((X >>u N) & 1) != 0 to BT(X, N).
|
|
// Lower ((X >>s N) & 1) != 0 to BT(X, N).
|
|
if (Op0.getOpcode() == ISD::AND &&
|
|
Op0.hasOneUse() &&
|
|
Op1.getOpcode() == ISD::Constant &&
|
|
cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
|
|
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
|
|
SDValue LHS, RHS;
|
|
if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
|
|
if (ConstantSDNode *Op010C =
|
|
dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
|
|
if (Op010C->getZExtValue() == 1) {
|
|
LHS = Op0.getOperand(0);
|
|
RHS = Op0.getOperand(1).getOperand(1);
|
|
}
|
|
} else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
|
|
if (ConstantSDNode *Op000C =
|
|
dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
|
|
if (Op000C->getZExtValue() == 1) {
|
|
LHS = Op0.getOperand(1);
|
|
RHS = Op0.getOperand(0).getOperand(1);
|
|
}
|
|
} else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
|
|
SDValue AndLHS = Op0.getOperand(0);
|
|
if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
|
|
LHS = AndLHS.getOperand(0);
|
|
RHS = AndLHS.getOperand(1);
|
|
}
|
|
}
|
|
|
|
if (LHS.getNode()) {
|
|
// If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
|
|
// instruction. Since the shift amount is in-range-or-undefined, we know
|
|
// that doing a bittest on the i16 value is ok. We extend to i32 because
|
|
// the encoding for the i16 version is larger than the i32 version.
|
|
if (LHS.getValueType() == MVT::i8)
|
|
LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
|
|
|
|
// If the operand types disagree, extend the shift amount to match. Since
|
|
// BT ignores high bits (like shifts) we can use anyextend.
|
|
if (LHS.getValueType() != RHS.getValueType())
|
|
RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
|
|
|
|
SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
|
|
unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
|
|
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
|
|
DAG.getConstant(Cond, MVT::i8), BT);
|
|
}
|
|
}
|
|
|
|
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
|
|
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
|
|
|
|
SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
|
|
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
|
|
DAG.getConstant(X86CC, MVT::i8), Cond);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue Cond;
|
|
SDValue Op0 = Op.getOperand(0);
|
|
SDValue Op1 = Op.getOperand(1);
|
|
SDValue CC = Op.getOperand(2);
|
|
MVT VT = Op.getValueType();
|
|
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
|
|
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
if (isFP) {
|
|
unsigned SSECC = 8;
|
|
MVT VT0 = Op0.getValueType();
|
|
assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
|
|
unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
|
|
bool Swap = false;
|
|
|
|
switch (SetCCOpcode) {
|
|
default: break;
|
|
case ISD::SETOEQ:
|
|
case ISD::SETEQ: SSECC = 0; break;
|
|
case ISD::SETOGT:
|
|
case ISD::SETGT: Swap = true; // Fallthrough
|
|
case ISD::SETLT:
|
|
case ISD::SETOLT: SSECC = 1; break;
|
|
case ISD::SETOGE:
|
|
case ISD::SETGE: Swap = true; // Fallthrough
|
|
case ISD::SETLE:
|
|
case ISD::SETOLE: SSECC = 2; break;
|
|
case ISD::SETUO: SSECC = 3; break;
|
|
case ISD::SETUNE:
|
|
case ISD::SETNE: SSECC = 4; break;
|
|
case ISD::SETULE: Swap = true;
|
|
case ISD::SETUGE: SSECC = 5; break;
|
|
case ISD::SETULT: Swap = true;
|
|
case ISD::SETUGT: SSECC = 6; break;
|
|
case ISD::SETO: SSECC = 7; break;
|
|
}
|
|
if (Swap)
|
|
std::swap(Op0, Op1);
|
|
|
|
// In the two special cases we can't handle, emit two comparisons.
|
|
if (SSECC == 8) {
|
|
if (SetCCOpcode == ISD::SETUEQ) {
|
|
SDValue UNORD, EQ;
|
|
UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
|
|
EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
|
|
return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
|
|
}
|
|
else if (SetCCOpcode == ISD::SETONE) {
|
|
SDValue ORD, NEQ;
|
|
ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
|
|
NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
|
|
return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
|
|
}
|
|
assert(0 && "Illegal FP comparison");
|
|
}
|
|
// Handle all other FP comparisons here.
|
|
return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
|
|
}
|
|
|
|
// We are handling one of the integer comparisons here. Since SSE only has
|
|
// GT and EQ comparisons for integer, swapping operands and multiple
|
|
// operations may be required for some comparisons.
|
|
unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
|
|
bool Swap = false, Invert = false, FlipSigns = false;
|
|
|
|
switch (VT.getSimpleVT()) {
|
|
default: break;
|
|
case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
|
|
case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
|
|
case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
|
|
case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
|
|
}
|
|
|
|
switch (SetCCOpcode) {
|
|
default: break;
|
|
case ISD::SETNE: Invert = true;
|
|
case ISD::SETEQ: Opc = EQOpc; break;
|
|
case ISD::SETLT: Swap = true;
|
|
case ISD::SETGT: Opc = GTOpc; break;
|
|
case ISD::SETGE: Swap = true;
|
|
case ISD::SETLE: Opc = GTOpc; Invert = true; break;
|
|
case ISD::SETULT: Swap = true;
|
|
case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
|
|
case ISD::SETUGE: Swap = true;
|
|
case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
|
|
}
|
|
if (Swap)
|
|
std::swap(Op0, Op1);
|
|
|
|
// Since SSE has no unsigned integer comparisons, we need to flip the sign
|
|
// bits of the inputs before performing those operations.
|
|
if (FlipSigns) {
|
|
MVT EltVT = VT.getVectorElementType();
|
|
SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
|
|
EltVT);
|
|
std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
|
|
SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
|
|
SignBits.size());
|
|
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
|
|
Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
|
|
}
|
|
|
|
SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
|
|
|
|
// If the logical-not of the result is required, perform that now.
|
|
if (Invert)
|
|
Result = DAG.getNOT(dl, Result, VT);
|
|
|
|
return Result;
|
|
}
|
|
|
|
// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
|
|
static bool isX86LogicalCmp(SDValue Op) {
|
|
unsigned Opc = Op.getNode()->getOpcode();
|
|
if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
|
|
return true;
|
|
if (Op.getResNo() == 1 &&
|
|
(Opc == X86ISD::ADD ||
|
|
Opc == X86ISD::SUB ||
|
|
Opc == X86ISD::SMUL ||
|
|
Opc == X86ISD::UMUL ||
|
|
Opc == X86ISD::INC ||
|
|
Opc == X86ISD::DEC))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
|
|
bool addTest = true;
|
|
SDValue Cond = Op.getOperand(0);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue CC;
|
|
|
|
if (Cond.getOpcode() == ISD::SETCC)
|
|
Cond = LowerSETCC(Cond, DAG);
|
|
|
|
// If condition flag is set by a X86ISD::CMP, then use it as the condition
|
|
// setting operand in place of the X86ISD::SETCC.
|
|
if (Cond.getOpcode() == X86ISD::SETCC) {
|
|
CC = Cond.getOperand(0);
|
|
|
|
SDValue Cmp = Cond.getOperand(1);
|
|
unsigned Opc = Cmp.getOpcode();
|
|
MVT VT = Op.getValueType();
|
|
|
|
bool IllegalFPCMov = false;
|
|
if (VT.isFloatingPoint() && !VT.isVector() &&
|
|
!isScalarFPTypeInSSEReg(VT)) // FPStack?
|
|
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
|
|
|
|
if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
|
|
Opc == X86ISD::BT) { // FIXME
|
|
Cond = Cmp;
|
|
addTest = false;
|
|
}
|
|
}
|
|
|
|
if (addTest) {
|
|
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
|
|
Cond = EmitTest(Cond, X86::COND_NE, DAG);
|
|
}
|
|
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
|
|
SmallVector<SDValue, 4> Ops;
|
|
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
|
|
// condition is true.
|
|
Ops.push_back(Op.getOperand(2));
|
|
Ops.push_back(Op.getOperand(1));
|
|
Ops.push_back(CC);
|
|
Ops.push_back(Cond);
|
|
return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
|
|
}
|
|
|
|
// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
|
|
// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
|
|
// from the AND / OR.
|
|
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
|
|
Opc = Op.getOpcode();
|
|
if (Opc != ISD::OR && Opc != ISD::AND)
|
|
return false;
|
|
return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
|
|
Op.getOperand(0).hasOneUse() &&
|
|
Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
|
|
Op.getOperand(1).hasOneUse());
|
|
}
|
|
|
|
// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
|
|
// 1 and that the SETCC node has a single use.
|
|
static bool isXor1OfSetCC(SDValue Op) {
|
|
if (Op.getOpcode() != ISD::XOR)
|
|
return false;
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
|
|
if (N1C && N1C->getAPIntValue() == 1) {
|
|
return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
|
|
Op.getOperand(0).hasOneUse();
|
|
}
|
|
return false;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
|
|
bool addTest = true;
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue Cond = Op.getOperand(1);
|
|
SDValue Dest = Op.getOperand(2);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue CC;
|
|
|
|
if (Cond.getOpcode() == ISD::SETCC)
|
|
Cond = LowerSETCC(Cond, DAG);
|
|
#if 0
|
|
// FIXME: LowerXALUO doesn't handle these!!
|
|
else if (Cond.getOpcode() == X86ISD::ADD ||
|
|
Cond.getOpcode() == X86ISD::SUB ||
|
|
Cond.getOpcode() == X86ISD::SMUL ||
|
|
Cond.getOpcode() == X86ISD::UMUL)
|
|
Cond = LowerXALUO(Cond, DAG);
|
|
#endif
|
|
|
|
// If condition flag is set by a X86ISD::CMP, then use it as the condition
|
|
// setting operand in place of the X86ISD::SETCC.
|
|
if (Cond.getOpcode() == X86ISD::SETCC) {
|
|
CC = Cond.getOperand(0);
|
|
|
|
SDValue Cmp = Cond.getOperand(1);
|
|
unsigned Opc = Cmp.getOpcode();
|
|
// FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
|
|
if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
|
|
Cond = Cmp;
|
|
addTest = false;
|
|
} else {
|
|
switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
|
|
default: break;
|
|
case X86::COND_O:
|
|
case X86::COND_B:
|
|
// These can only come from an arithmetic instruction with overflow,
|
|
// e.g. SADDO, UADDO.
|
|
Cond = Cond.getNode()->getOperand(1);
|
|
addTest = false;
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
unsigned CondOpc;
|
|
if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
|
|
SDValue Cmp = Cond.getOperand(0).getOperand(1);
|
|
if (CondOpc == ISD::OR) {
|
|
// Also, recognize the pattern generated by an FCMP_UNE. We can emit
|
|
// two branches instead of an explicit OR instruction with a
|
|
// separate test.
|
|
if (Cmp == Cond.getOperand(1).getOperand(1) &&
|
|
isX86LogicalCmp(Cmp)) {
|
|
CC = Cond.getOperand(0).getOperand(0);
|
|
Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
|
|
Chain, Dest, CC, Cmp);
|
|
CC = Cond.getOperand(1).getOperand(0);
|
|
Cond = Cmp;
|
|
addTest = false;
|
|
}
|
|
} else { // ISD::AND
|
|
// Also, recognize the pattern generated by an FCMP_OEQ. We can emit
|
|
// two branches instead of an explicit AND instruction with a
|
|
// separate test. However, we only do this if this block doesn't
|
|
// have a fall-through edge, because this requires an explicit
|
|
// jmp when the condition is false.
|
|
if (Cmp == Cond.getOperand(1).getOperand(1) &&
|
|
isX86LogicalCmp(Cmp) &&
|
|
Op.getNode()->hasOneUse()) {
|
|
X86::CondCode CCode =
|
|
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
|
|
CCode = X86::GetOppositeBranchCondition(CCode);
|
|
CC = DAG.getConstant(CCode, MVT::i8);
|
|
SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
|
|
// Look for an unconditional branch following this conditional branch.
|
|
// We need this because we need to reverse the successors in order
|
|
// to implement FCMP_OEQ.
|
|
if (User.getOpcode() == ISD::BR) {
|
|
SDValue FalseBB = User.getOperand(1);
|
|
SDValue NewBR =
|
|
DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
|
|
assert(NewBR == User);
|
|
Dest = FalseBB;
|
|
|
|
Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
|
|
Chain, Dest, CC, Cmp);
|
|
X86::CondCode CCode =
|
|
(X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
|
|
CCode = X86::GetOppositeBranchCondition(CCode);
|
|
CC = DAG.getConstant(CCode, MVT::i8);
|
|
Cond = Cmp;
|
|
addTest = false;
|
|
}
|
|
}
|
|
}
|
|
} else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
|
|
// Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
|
|
// It should be transformed during dag combiner except when the condition
|
|
// is set by a arithmetics with overflow node.
|
|
X86::CondCode CCode =
|
|
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
|
|
CCode = X86::GetOppositeBranchCondition(CCode);
|
|
CC = DAG.getConstant(CCode, MVT::i8);
|
|
Cond = Cond.getOperand(0).getOperand(1);
|
|
addTest = false;
|
|
}
|
|
}
|
|
|
|
if (addTest) {
|
|
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
|
|
Cond = EmitTest(Cond, X86::COND_NE, DAG);
|
|
}
|
|
return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
|
|
Chain, Dest, CC, Cond);
|
|
}
|
|
|
|
|
|
// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
|
|
// Calls to _alloca is needed to probe the stack when allocating more than 4k
|
|
// bytes in one go. Touching the stack at 4K increments is necessary to ensure
|
|
// that the guard pages used by the OS virtual memory manager are allocated in
|
|
// correct sequence.
|
|
SDValue
|
|
X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
assert(Subtarget->isTargetCygMing() &&
|
|
"This should be used only on Cygwin/Mingw targets");
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
// Get the inputs.
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue Size = Op.getOperand(1);
|
|
// FIXME: Ensure alignment here
|
|
|
|
SDValue Flag;
|
|
|
|
MVT IntPtr = getPointerTy();
|
|
MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
|
|
|
|
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
|
|
Flag = Chain.getValue(1);
|
|
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SDValue Ops[] = { Chain,
|
|
DAG.getTargetExternalSymbol("_alloca", IntPtr),
|
|
DAG.getRegister(X86::EAX, IntPtr),
|
|
DAG.getRegister(X86StackPtr, SPTy),
|
|
Flag };
|
|
Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
|
|
Flag = Chain.getValue(1);
|
|
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
DAG.getIntPtrConstant(0, true),
|
|
DAG.getIntPtrConstant(0, true),
|
|
Flag);
|
|
|
|
Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
|
|
|
|
SDValue Ops1[2] = { Chain.getValue(0), Chain };
|
|
return DAG.getMergeValues(Ops1, 2, dl);
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
|
|
SDValue Chain,
|
|
SDValue Dst, SDValue Src,
|
|
SDValue Size, unsigned Align,
|
|
const Value *DstSV,
|
|
uint64_t DstSVOff) {
|
|
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
|
|
|
|
// If not DWORD aligned or size is more than the threshold, call the library.
|
|
// The libc version is likely to be faster for these cases. It can use the
|
|
// address value and run time information about the CPU.
|
|
if ((Align & 3) != 0 ||
|
|
!ConstantSize ||
|
|
ConstantSize->getZExtValue() >
|
|
getSubtarget()->getMaxInlineSizeThreshold()) {
|
|
SDValue InFlag(0, 0);
|
|
|
|
// Check to see if there is a specialized entry-point for memory zeroing.
|
|
ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
|
|
|
|
if (const char *bzeroEntry = V &&
|
|
V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
|
|
MVT IntPtr = getPointerTy();
|
|
const Type *IntPtrTy = TD->getIntPtrType();
|
|
TargetLowering::ArgListTy Args;
|
|
TargetLowering::ArgListEntry Entry;
|
|
Entry.Node = Dst;
|
|
Entry.Ty = IntPtrTy;
|
|
Args.push_back(Entry);
|
|
Entry.Node = Size;
|
|
Args.push_back(Entry);
|
|
std::pair<SDValue,SDValue> CallResult =
|
|
LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
|
|
CallingConv::C, false,
|
|
DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
|
|
return CallResult.second;
|
|
}
|
|
|
|
// Otherwise have the target-independent code call memset.
|
|
return SDValue();
|
|
}
|
|
|
|
uint64_t SizeVal = ConstantSize->getZExtValue();
|
|
SDValue InFlag(0, 0);
|
|
MVT AVT;
|
|
SDValue Count;
|
|
ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
|
|
unsigned BytesLeft = 0;
|
|
bool TwoRepStos = false;
|
|
if (ValC) {
|
|
unsigned ValReg;
|
|
uint64_t Val = ValC->getZExtValue() & 255;
|
|
|
|
// If the value is a constant, then we can potentially use larger sets.
|
|
switch (Align & 3) {
|
|
case 2: // WORD aligned
|
|
AVT = MVT::i16;
|
|
ValReg = X86::AX;
|
|
Val = (Val << 8) | Val;
|
|
break;
|
|
case 0: // DWORD aligned
|
|
AVT = MVT::i32;
|
|
ValReg = X86::EAX;
|
|
Val = (Val << 8) | Val;
|
|
Val = (Val << 16) | Val;
|
|
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
|
|
AVT = MVT::i64;
|
|
ValReg = X86::RAX;
|
|
Val = (Val << 32) | Val;
|
|
}
|
|
break;
|
|
default: // Byte aligned
|
|
AVT = MVT::i8;
|
|
ValReg = X86::AL;
|
|
Count = DAG.getIntPtrConstant(SizeVal);
|
|
break;
|
|
}
|
|
|
|
if (AVT.bitsGT(MVT::i8)) {
|
|
unsigned UBytes = AVT.getSizeInBits() / 8;
|
|
Count = DAG.getIntPtrConstant(SizeVal / UBytes);
|
|
BytesLeft = SizeVal % UBytes;
|
|
}
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
|
|
InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
} else {
|
|
AVT = MVT::i8;
|
|
Count = DAG.getIntPtrConstant(SizeVal);
|
|
Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
|
|
X86::ECX,
|
|
Count, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
|
|
X86::EDI,
|
|
Dst, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(DAG.getValueType(AVT));
|
|
Ops.push_back(InFlag);
|
|
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
|
|
|
|
if (TwoRepStos) {
|
|
InFlag = Chain.getValue(1);
|
|
Count = Size;
|
|
MVT CVT = Count.getValueType();
|
|
SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
|
|
DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
|
|
Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
|
|
X86::ECX,
|
|
Left, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
Ops.clear();
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(DAG.getValueType(MVT::i8));
|
|
Ops.push_back(InFlag);
|
|
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
|
|
} else if (BytesLeft) {
|
|
// Handle the last 1 - 7 bytes.
|
|
unsigned Offset = SizeVal - BytesLeft;
|
|
MVT AddrVT = Dst.getValueType();
|
|
MVT SizeVT = Size.getValueType();
|
|
|
|
Chain = DAG.getMemset(Chain, dl,
|
|
DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
|
|
DAG.getConstant(Offset, AddrVT)),
|
|
Src,
|
|
DAG.getConstant(BytesLeft, SizeVT),
|
|
Align, DstSV, DstSVOff + Offset);
|
|
}
|
|
|
|
// TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
|
|
return Chain;
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
|
|
SDValue Chain, SDValue Dst, SDValue Src,
|
|
SDValue Size, unsigned Align,
|
|
bool AlwaysInline,
|
|
const Value *DstSV, uint64_t DstSVOff,
|
|
const Value *SrcSV, uint64_t SrcSVOff) {
|
|
// This requires the copy size to be a constant, preferrably
|
|
// within a subtarget-specific limit.
|
|
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
|
|
if (!ConstantSize)
|
|
return SDValue();
|
|
uint64_t SizeVal = ConstantSize->getZExtValue();
|
|
if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
|
|
return SDValue();
|
|
|
|
/// If not DWORD aligned, call the library.
|
|
if ((Align & 3) != 0)
|
|
return SDValue();
|
|
|
|
// DWORD aligned
|
|
MVT AVT = MVT::i32;
|
|
if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
|
|
AVT = MVT::i64;
|
|
|
|
unsigned UBytes = AVT.getSizeInBits() / 8;
|
|
unsigned CountVal = SizeVal / UBytes;
|
|
SDValue Count = DAG.getIntPtrConstant(CountVal);
|
|
unsigned BytesLeft = SizeVal % UBytes;
|
|
|
|
SDValue InFlag(0, 0);
|
|
Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
|
|
X86::ECX,
|
|
Count, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
|
|
X86::EDI,
|
|
Dst, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
|
|
X86::ESI,
|
|
Src, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(DAG.getValueType(AVT));
|
|
Ops.push_back(InFlag);
|
|
SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
|
|
|
|
SmallVector<SDValue, 4> Results;
|
|
Results.push_back(RepMovs);
|
|
if (BytesLeft) {
|
|
// Handle the last 1 - 7 bytes.
|
|
unsigned Offset = SizeVal - BytesLeft;
|
|
MVT DstVT = Dst.getValueType();
|
|
MVT SrcVT = Src.getValueType();
|
|
MVT SizeVT = Size.getValueType();
|
|
Results.push_back(DAG.getMemcpy(Chain, dl,
|
|
DAG.getNode(ISD::ADD, dl, DstVT, Dst,
|
|
DAG.getConstant(Offset, DstVT)),
|
|
DAG.getNode(ISD::ADD, dl, SrcVT, Src,
|
|
DAG.getConstant(Offset, SrcVT)),
|
|
DAG.getConstant(BytesLeft, SizeVT),
|
|
Align, AlwaysInline,
|
|
DstSV, DstSVOff + Offset,
|
|
SrcSV, SrcSVOff + Offset));
|
|
}
|
|
|
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&Results[0], Results.size());
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
if (!Subtarget->is64Bit()) {
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
// memory location argument.
|
|
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
|
|
return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
|
|
}
|
|
|
|
// __va_list_tag:
|
|
// gp_offset (0 - 6 * 8)
|
|
// fp_offset (48 - 48 + 8 * 16)
|
|
// overflow_arg_area (point to parameters coming in memory).
|
|
// reg_save_area
|
|
SmallVector<SDValue, 8> MemOps;
|
|
SDValue FIN = Op.getOperand(1);
|
|
// Store gp_offset
|
|
SDValue Store = DAG.getStore(Op.getOperand(0), dl,
|
|
DAG.getConstant(VarArgsGPOffset, MVT::i32),
|
|
FIN, SV, 0);
|
|
MemOps.push_back(Store);
|
|
|
|
// Store fp_offset
|
|
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
FIN, DAG.getIntPtrConstant(4));
|
|
Store = DAG.getStore(Op.getOperand(0), dl,
|
|
DAG.getConstant(VarArgsFPOffset, MVT::i32),
|
|
FIN, SV, 0);
|
|
MemOps.push_back(Store);
|
|
|
|
// Store ptr to overflow_arg_area
|
|
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
FIN, DAG.getIntPtrConstant(4));
|
|
SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
|
|
Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
|
|
MemOps.push_back(Store);
|
|
|
|
// Store ptr to reg_save_area.
|
|
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
FIN, DAG.getIntPtrConstant(8));
|
|
SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
|
Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
|
|
MemOps.push_back(Store);
|
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&MemOps[0], MemOps.size());
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
|
|
// X86-64 va_list is a struct { i32, i32, i8*, i8* }.
|
|
assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue SrcPtr = Op.getOperand(1);
|
|
SDValue SrcSV = Op.getOperand(2);
|
|
|
|
assert(0 && "VAArgInst is not yet implemented for x86-64!");
|
|
abort();
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
|
|
// X86-64 va_list is a struct { i32, i32, i8*, i8* }.
|
|
assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue DstPtr = Op.getOperand(1);
|
|
SDValue SrcPtr = Op.getOperand(2);
|
|
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
|
|
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
|
|
DAG.getIntPtrConstant(24), 8, false,
|
|
DstSV, 0, SrcSV, 0);
|
|
}
|
|
|
|
SDValue
|
|
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
|
switch (IntNo) {
|
|
default: return SDValue(); // Don't custom lower most intrinsics.
|
|
// Comparison intrinsics.
|
|
case Intrinsic::x86_sse_comieq_ss:
|
|
case Intrinsic::x86_sse_comilt_ss:
|
|
case Intrinsic::x86_sse_comile_ss:
|
|
case Intrinsic::x86_sse_comigt_ss:
|
|
case Intrinsic::x86_sse_comige_ss:
|
|
case Intrinsic::x86_sse_comineq_ss:
|
|
case Intrinsic::x86_sse_ucomieq_ss:
|
|
case Intrinsic::x86_sse_ucomilt_ss:
|
|
case Intrinsic::x86_sse_ucomile_ss:
|
|
case Intrinsic::x86_sse_ucomigt_ss:
|
|
case Intrinsic::x86_sse_ucomige_ss:
|
|
case Intrinsic::x86_sse_ucomineq_ss:
|
|
case Intrinsic::x86_sse2_comieq_sd:
|
|
case Intrinsic::x86_sse2_comilt_sd:
|
|
case Intrinsic::x86_sse2_comile_sd:
|
|
case Intrinsic::x86_sse2_comigt_sd:
|
|
case Intrinsic::x86_sse2_comige_sd:
|
|
case Intrinsic::x86_sse2_comineq_sd:
|
|
case Intrinsic::x86_sse2_ucomieq_sd:
|
|
case Intrinsic::x86_sse2_ucomilt_sd:
|
|
case Intrinsic::x86_sse2_ucomile_sd:
|
|
case Intrinsic::x86_sse2_ucomigt_sd:
|
|
case Intrinsic::x86_sse2_ucomige_sd:
|
|
case Intrinsic::x86_sse2_ucomineq_sd: {
|
|
unsigned Opc = 0;
|
|
ISD::CondCode CC = ISD::SETCC_INVALID;
|
|
switch (IntNo) {
|
|
default: break;
|
|
case Intrinsic::x86_sse_comieq_ss:
|
|
case Intrinsic::x86_sse2_comieq_sd:
|
|
Opc = X86ISD::COMI;
|
|
CC = ISD::SETEQ;
|
|
break;
|
|
case Intrinsic::x86_sse_comilt_ss:
|
|
case Intrinsic::x86_sse2_comilt_sd:
|
|
Opc = X86ISD::COMI;
|
|
CC = ISD::SETLT;
|
|
break;
|
|
case Intrinsic::x86_sse_comile_ss:
|
|
case Intrinsic::x86_sse2_comile_sd:
|
|
Opc = X86ISD::COMI;
|
|
CC = ISD::SETLE;
|
|
break;
|
|
case Intrinsic::x86_sse_comigt_ss:
|
|
case Intrinsic::x86_sse2_comigt_sd:
|
|
Opc = X86ISD::COMI;
|
|
CC = ISD::SETGT;
|
|
break;
|
|
case Intrinsic::x86_sse_comige_ss:
|
|
case Intrinsic::x86_sse2_comige_sd:
|
|
Opc = X86ISD::COMI;
|
|
CC = ISD::SETGE;
|
|
break;
|
|
case Intrinsic::x86_sse_comineq_ss:
|
|
case Intrinsic::x86_sse2_comineq_sd:
|
|
Opc = X86ISD::COMI;
|
|
CC = ISD::SETNE;
|
|
break;
|
|
case Intrinsic::x86_sse_ucomieq_ss:
|
|
case Intrinsic::x86_sse2_ucomieq_sd:
|
|
Opc = X86ISD::UCOMI;
|
|
CC = ISD::SETEQ;
|
|
break;
|
|
case Intrinsic::x86_sse_ucomilt_ss:
|
|
case Intrinsic::x86_sse2_ucomilt_sd:
|
|
Opc = X86ISD::UCOMI;
|
|
CC = ISD::SETLT;
|
|
break;
|
|
case Intrinsic::x86_sse_ucomile_ss:
|
|
case Intrinsic::x86_sse2_ucomile_sd:
|
|
Opc = X86ISD::UCOMI;
|
|
CC = ISD::SETLE;
|
|
break;
|
|
case Intrinsic::x86_sse_ucomigt_ss:
|
|
case Intrinsic::x86_sse2_ucomigt_sd:
|
|
Opc = X86ISD::UCOMI;
|
|
CC = ISD::SETGT;
|
|
break;
|
|
case Intrinsic::x86_sse_ucomige_ss:
|
|
case Intrinsic::x86_sse2_ucomige_sd:
|
|
Opc = X86ISD::UCOMI;
|
|
CC = ISD::SETGE;
|
|
break;
|
|
case Intrinsic::x86_sse_ucomineq_ss:
|
|
case Intrinsic::x86_sse2_ucomineq_sd:
|
|
Opc = X86ISD::UCOMI;
|
|
CC = ISD::SETNE;
|
|
break;
|
|
}
|
|
|
|
SDValue LHS = Op.getOperand(1);
|
|
SDValue RHS = Op.getOperand(2);
|
|
unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
|
|
SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
|
|
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
|
|
DAG.getConstant(X86CC, MVT::i8), Cond);
|
|
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
|
|
}
|
|
|
|
// Fix vector shift instructions where the last operand is a non-immediate
|
|
// i32 value.
|
|
case Intrinsic::x86_sse2_pslli_w:
|
|
case Intrinsic::x86_sse2_pslli_d:
|
|
case Intrinsic::x86_sse2_pslli_q:
|
|
case Intrinsic::x86_sse2_psrli_w:
|
|
case Intrinsic::x86_sse2_psrli_d:
|
|
case Intrinsic::x86_sse2_psrli_q:
|
|
case Intrinsic::x86_sse2_psrai_w:
|
|
case Intrinsic::x86_sse2_psrai_d:
|
|
case Intrinsic::x86_mmx_pslli_w:
|
|
case Intrinsic::x86_mmx_pslli_d:
|
|
case Intrinsic::x86_mmx_pslli_q:
|
|
case Intrinsic::x86_mmx_psrli_w:
|
|
case Intrinsic::x86_mmx_psrli_d:
|
|
case Intrinsic::x86_mmx_psrli_q:
|
|
case Intrinsic::x86_mmx_psrai_w:
|
|
case Intrinsic::x86_mmx_psrai_d: {
|
|
SDValue ShAmt = Op.getOperand(2);
|
|
if (isa<ConstantSDNode>(ShAmt))
|
|
return SDValue();
|
|
|
|
unsigned NewIntNo = 0;
|
|
MVT ShAmtVT = MVT::v4i32;
|
|
switch (IntNo) {
|
|
case Intrinsic::x86_sse2_pslli_w:
|
|
NewIntNo = Intrinsic::x86_sse2_psll_w;
|
|
break;
|
|
case Intrinsic::x86_sse2_pslli_d:
|
|
NewIntNo = Intrinsic::x86_sse2_psll_d;
|
|
break;
|
|
case Intrinsic::x86_sse2_pslli_q:
|
|
NewIntNo = Intrinsic::x86_sse2_psll_q;
|
|
break;
|
|
case Intrinsic::x86_sse2_psrli_w:
|
|
NewIntNo = Intrinsic::x86_sse2_psrl_w;
|
|
break;
|
|
case Intrinsic::x86_sse2_psrli_d:
|
|
NewIntNo = Intrinsic::x86_sse2_psrl_d;
|
|
break;
|
|
case Intrinsic::x86_sse2_psrli_q:
|
|
NewIntNo = Intrinsic::x86_sse2_psrl_q;
|
|
break;
|
|
case Intrinsic::x86_sse2_psrai_w:
|
|
NewIntNo = Intrinsic::x86_sse2_psra_w;
|
|
break;
|
|
case Intrinsic::x86_sse2_psrai_d:
|
|
NewIntNo = Intrinsic::x86_sse2_psra_d;
|
|
break;
|
|
default: {
|
|
ShAmtVT = MVT::v2i32;
|
|
switch (IntNo) {
|
|
case Intrinsic::x86_mmx_pslli_w:
|
|
NewIntNo = Intrinsic::x86_mmx_psll_w;
|
|
break;
|
|
case Intrinsic::x86_mmx_pslli_d:
|
|
NewIntNo = Intrinsic::x86_mmx_psll_d;
|
|
break;
|
|
case Intrinsic::x86_mmx_pslli_q:
|
|
NewIntNo = Intrinsic::x86_mmx_psll_q;
|
|
break;
|
|
case Intrinsic::x86_mmx_psrli_w:
|
|
NewIntNo = Intrinsic::x86_mmx_psrl_w;
|
|
break;
|
|
case Intrinsic::x86_mmx_psrli_d:
|
|
NewIntNo = Intrinsic::x86_mmx_psrl_d;
|
|
break;
|
|
case Intrinsic::x86_mmx_psrli_q:
|
|
NewIntNo = Intrinsic::x86_mmx_psrl_q;
|
|
break;
|
|
case Intrinsic::x86_mmx_psrai_w:
|
|
NewIntNo = Intrinsic::x86_mmx_psra_w;
|
|
break;
|
|
case Intrinsic::x86_mmx_psrai_d:
|
|
NewIntNo = Intrinsic::x86_mmx_psra_d;
|
|
break;
|
|
default: abort(); // Can't reach here.
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
MVT VT = Op.getValueType();
|
|
ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
|
|
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(NewIntNo, MVT::i32),
|
|
Op.getOperand(1), ShAmt);
|
|
}
|
|
}
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
|
|
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
if (Depth > 0) {
|
|
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
|
|
SDValue Offset =
|
|
DAG.getConstant(TD->getPointerSize(),
|
|
Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
|
|
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
|
|
DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
FrameAddr, Offset),
|
|
NULL, 0);
|
|
}
|
|
|
|
// Just load the return address.
|
|
SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
|
|
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
|
|
RetAddrFI, NULL, 0);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
|
|
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
|
MFI->setFrameAddressIsTaken(true);
|
|
MVT VT = Op.getValueType();
|
|
DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
|
|
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
|
unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
|
|
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
|
|
while (Depth--)
|
|
FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
|
|
return FrameAddr;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
return DAG.getIntPtrConstant(2*TD->getPointerSize());
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
|
|
{
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue Offset = Op.getOperand(1);
|
|
SDValue Handler = Op.getOperand(2);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
|
|
getPointerTy());
|
|
unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
|
|
|
|
SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
|
|
DAG.getIntPtrConstant(-TD->getPointerSize()));
|
|
StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
|
|
Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
|
|
Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
|
|
MF.getRegInfo().addLiveOut(StoreAddrReg);
|
|
|
|
return DAG.getNode(X86ISD::EH_RETURN, dl,
|
|
MVT::Other,
|
|
Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
SDValue Root = Op.getOperand(0);
|
|
SDValue Trmp = Op.getOperand(1); // trampoline
|
|
SDValue FPtr = Op.getOperand(2); // nested function
|
|
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
|
|
|
const X86InstrInfo *TII =
|
|
((X86TargetMachine&)getTargetMachine()).getInstrInfo();
|
|
|
|
if (Subtarget->is64Bit()) {
|
|
SDValue OutChains[6];
|
|
|
|
// Large code-model.
|
|
|
|
const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
|
|
const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
|
|
|
|
const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
|
|
const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
|
|
|
|
const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
|
|
|
|
// Load the pointer to the nested function into R11.
|
|
unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
|
|
SDValue Addr = Trmp;
|
|
OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
|
|
Addr, TrmpAddr, 0);
|
|
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
|
|
DAG.getConstant(2, MVT::i64));
|
|
OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
|
|
|
|
// Load the 'nest' parameter value into R10.
|
|
// R10 is specified in X86CallingConv.td
|
|
OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
|
|
DAG.getConstant(10, MVT::i64));
|
|
OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
|
|
Addr, TrmpAddr, 10);
|
|
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
|
|
DAG.getConstant(12, MVT::i64));
|
|
OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
|
|
|
|
// Jump to the nested function.
|
|
OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
|
|
DAG.getConstant(20, MVT::i64));
|
|
OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
|
|
Addr, TrmpAddr, 20);
|
|
|
|
unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
|
|
DAG.getConstant(22, MVT::i64));
|
|
OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
|
|
TrmpAddr, 22);
|
|
|
|
SDValue Ops[] =
|
|
{ Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
|
|
return DAG.getMergeValues(Ops, 2, dl);
|
|
} else {
|
|
const Function *Func =
|
|
cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
|
|
unsigned CC = Func->getCallingConv();
|
|
unsigned NestReg;
|
|
|
|
switch (CC) {
|
|
default:
|
|
assert(0 && "Unsupported calling convention");
|
|
case CallingConv::C:
|
|
case CallingConv::X86_StdCall: {
|
|
// Pass 'nest' parameter in ECX.
|
|
// Must be kept in sync with X86CallingConv.td
|
|
NestReg = X86::ECX;
|
|
|
|
// Check that ECX wasn't needed by an 'inreg' parameter.
|
|
const FunctionType *FTy = Func->getFunctionType();
|
|
const AttrListPtr &Attrs = Func->getAttributes();
|
|
|
|
if (!Attrs.isEmpty() && !Func->isVarArg()) {
|
|
unsigned InRegCount = 0;
|
|
unsigned Idx = 1;
|
|
|
|
for (FunctionType::param_iterator I = FTy->param_begin(),
|
|
E = FTy->param_end(); I != E; ++I, ++Idx)
|
|
if (Attrs.paramHasAttr(Idx, Attribute::InReg))
|
|
// FIXME: should only count parameters that are lowered to integers.
|
|
InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
|
|
|
|
if (InRegCount > 2) {
|
|
cerr << "Nest register in use - reduce number of inreg parameters!\n";
|
|
abort();
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case CallingConv::X86_FastCall:
|
|
case CallingConv::Fast:
|
|
// Pass 'nest' parameter in EAX.
|
|
// Must be kept in sync with X86CallingConv.td
|
|
NestReg = X86::EAX;
|
|
break;
|
|
}
|
|
|
|
SDValue OutChains[4];
|
|
SDValue Addr, Disp;
|
|
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
|
|
DAG.getConstant(10, MVT::i32));
|
|
Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
|
|
|
|
const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
|
|
const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
|
|
OutChains[0] = DAG.getStore(Root, dl,
|
|
DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
|
|
Trmp, TrmpAddr, 0);
|
|
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
|
|
DAG.getConstant(1, MVT::i32));
|
|
OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
|
|
|
|
const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
|
|
DAG.getConstant(5, MVT::i32));
|
|
OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
|
|
TrmpAddr, 5, false, 1);
|
|
|
|
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
|
|
DAG.getConstant(6, MVT::i32));
|
|
OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
|
|
|
|
SDValue Ops[] =
|
|
{ Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
|
|
return DAG.getMergeValues(Ops, 2, dl);
|
|
}
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
|
|
/*
|
|
The rounding mode is in bits 11:10 of FPSR, and has the following
|
|
settings:
|
|
00 Round to nearest
|
|
01 Round to -inf
|
|
10 Round to +inf
|
|
11 Round to 0
|
|
|
|
FLT_ROUNDS, on the other hand, expects the following:
|
|
-1 Undefined
|
|
0 Round to 0
|
|
1 Round to nearest
|
|
2 Round to +inf
|
|
3 Round to -inf
|
|
|
|
To perform the conversion, we do:
|
|
(((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
|
|
*/
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetFrameInfo &TFI = *TM.getFrameInfo();
|
|
unsigned StackAlignment = TFI.getStackAlignment();
|
|
MVT VT = Op.getValueType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
// Save FP Control Word to stack slot
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
|
|
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
|
|
DAG.getEntryNode(), StackSlot);
|
|
|
|
// Load FP Control Word from stack slot
|
|
SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
|
|
|
|
// Transform as necessary
|
|
SDValue CWD1 =
|
|
DAG.getNode(ISD::SRL, dl, MVT::i16,
|
|
DAG.getNode(ISD::AND, dl, MVT::i16,
|
|
CWD, DAG.getConstant(0x800, MVT::i16)),
|
|
DAG.getConstant(11, MVT::i8));
|
|
SDValue CWD2 =
|
|
DAG.getNode(ISD::SRL, dl, MVT::i16,
|
|
DAG.getNode(ISD::AND, dl, MVT::i16,
|
|
CWD, DAG.getConstant(0x400, MVT::i16)),
|
|
DAG.getConstant(9, MVT::i8));
|
|
|
|
SDValue RetVal =
|
|
DAG.getNode(ISD::AND, dl, MVT::i16,
|
|
DAG.getNode(ISD::ADD, dl, MVT::i16,
|
|
DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
|
|
DAG.getConstant(1, MVT::i16)),
|
|
DAG.getConstant(3, MVT::i16));
|
|
|
|
|
|
return DAG.getNode((VT.getSizeInBits() < 16 ?
|
|
ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
|
|
MVT VT = Op.getValueType();
|
|
MVT OpVT = VT;
|
|
unsigned NumBits = VT.getSizeInBits();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
Op = Op.getOperand(0);
|
|
if (VT == MVT::i8) {
|
|
// Zero extend to i32 since there is not an i8 bsr.
|
|
OpVT = MVT::i32;
|
|
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
|
|
}
|
|
|
|
// Issue a bsr (scan bits in reverse) which also sets EFLAGS.
|
|
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
|
|
Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
|
|
|
|
// If src is zero (i.e. bsr sets ZF), returns NumBits.
|
|
SmallVector<SDValue, 4> Ops;
|
|
Ops.push_back(Op);
|
|
Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
|
|
Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
|
|
Ops.push_back(Op.getValue(1));
|
|
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
|
|
|
|
// Finally xor with NumBits-1.
|
|
Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
|
|
|
|
if (VT == MVT::i8)
|
|
Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
|
|
return Op;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
|
|
MVT VT = Op.getValueType();
|
|
MVT OpVT = VT;
|
|
unsigned NumBits = VT.getSizeInBits();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
Op = Op.getOperand(0);
|
|
if (VT == MVT::i8) {
|
|
OpVT = MVT::i32;
|
|
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
|
|
}
|
|
|
|
// Issue a bsf (scan bits forward) which also sets EFLAGS.
|
|
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
|
|
Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
|
|
|
|
// If src is zero (i.e. bsf sets ZF), returns NumBits.
|
|
SmallVector<SDValue, 4> Ops;
|
|
Ops.push_back(Op);
|
|
Ops.push_back(DAG.getConstant(NumBits, OpVT));
|
|
Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
|
|
Ops.push_back(Op.getValue(1));
|
|
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
|
|
|
|
if (VT == MVT::i8)
|
|
Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
|
|
return Op;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
|
|
MVT VT = Op.getValueType();
|
|
assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
// ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
|
|
// ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
|
|
// ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
|
|
// ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
|
|
// ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
|
|
//
|
|
// AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
|
|
// AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
|
|
// return AloBlo + AloBhi + AhiBlo;
|
|
|
|
SDValue A = Op.getOperand(0);
|
|
SDValue B = Op.getOperand(1);
|
|
|
|
SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
|
|
A, DAG.getConstant(32, MVT::i32));
|
|
SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
|
|
B, DAG.getConstant(32, MVT::i32));
|
|
SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
|
|
A, B);
|
|
SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
|
|
A, Bhi);
|
|
SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
|
|
Ahi, B);
|
|
AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
|
|
AloBhi, DAG.getConstant(32, MVT::i32));
|
|
AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
|
|
AhiBlo, DAG.getConstant(32, MVT::i32));
|
|
SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
|
|
Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
|
|
return Res;
|
|
}
|
|
|
|
|
|
SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
|
|
// Lower the "add/sub/mul with overflow" instruction into a regular ins plus
|
|
// a "setcc" instruction that checks the overflow flag. The "brcond" lowering
|
|
// looks for this combo and may remove the "setcc" instruction if the "setcc"
|
|
// has only one use.
|
|
SDNode *N = Op.getNode();
|
|
SDValue LHS = N->getOperand(0);
|
|
SDValue RHS = N->getOperand(1);
|
|
unsigned BaseOp = 0;
|
|
unsigned Cond = 0;
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
switch (Op.getOpcode()) {
|
|
default: assert(0 && "Unknown ovf instruction!");
|
|
case ISD::SADDO:
|
|
// A subtract of one will be selected as a INC. Note that INC doesn't
|
|
// set CF, so we can't do this for UADDO.
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
|
|
if (C->getAPIntValue() == 1) {
|
|
BaseOp = X86ISD::INC;
|
|
Cond = X86::COND_O;
|
|
break;
|
|
}
|
|
BaseOp = X86ISD::ADD;
|
|
Cond = X86::COND_O;
|
|
break;
|
|
case ISD::UADDO:
|
|
BaseOp = X86ISD::ADD;
|
|
Cond = X86::COND_B;
|
|
break;
|
|
case ISD::SSUBO:
|
|
// A subtract of one will be selected as a DEC. Note that DEC doesn't
|
|
// set CF, so we can't do this for USUBO.
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
|
|
if (C->getAPIntValue() == 1) {
|
|
BaseOp = X86ISD::DEC;
|
|
Cond = X86::COND_O;
|
|
break;
|
|
}
|
|
BaseOp = X86ISD::SUB;
|
|
Cond = X86::COND_O;
|
|
break;
|
|
case ISD::USUBO:
|
|
BaseOp = X86ISD::SUB;
|
|
Cond = X86::COND_B;
|
|
break;
|
|
case ISD::SMULO:
|
|
BaseOp = X86ISD::SMUL;
|
|
Cond = X86::COND_O;
|
|
break;
|
|
case ISD::UMULO:
|
|
BaseOp = X86ISD::UMUL;
|
|
Cond = X86::COND_B;
|
|
break;
|
|
}
|
|
|
|
// Also sets EFLAGS.
|
|
SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
|
|
SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
|
|
|
|
SDValue SetCC =
|
|
DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
|
|
DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
|
|
|
|
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
|
|
return Sum;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
|
|
MVT T = Op.getValueType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
unsigned Reg = 0;
|
|
unsigned size = 0;
|
|
switch(T.getSimpleVT()) {
|
|
default:
|
|
assert(false && "Invalid value type!");
|
|
case MVT::i8: Reg = X86::AL; size = 1; break;
|
|
case MVT::i16: Reg = X86::AX; size = 2; break;
|
|
case MVT::i32: Reg = X86::EAX; size = 4; break;
|
|
case MVT::i64:
|
|
assert(Subtarget->is64Bit() && "Node not type legal!");
|
|
Reg = X86::RAX; size = 8;
|
|
break;
|
|
}
|
|
SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
|
|
Op.getOperand(2), SDValue());
|
|
SDValue Ops[] = { cpIn.getValue(0),
|
|
Op.getOperand(1),
|
|
Op.getOperand(3),
|
|
DAG.getTargetConstant(size, MVT::i8),
|
|
cpIn.getValue(1) };
|
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
|
|
SDValue cpOut =
|
|
DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
|
|
return cpOut;
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
assert(Subtarget->is64Bit() && "Result not type legalized?");
|
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SDValue TheChain = Op.getOperand(0);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
|
|
SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
|
|
SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
|
|
rax.getValue(2));
|
|
SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
|
|
DAG.getConstant(32, MVT::i8));
|
|
SDValue Ops[] = {
|
|
DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
|
|
rdx.getValue(1)
|
|
};
|
|
return DAG.getMergeValues(Ops, 2, dl);
|
|
}
|
|
|
|
SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
|
|
SDNode *Node = Op.getNode();
|
|
DebugLoc dl = Node->getDebugLoc();
|
|
MVT T = Node->getValueType(0);
|
|
SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
|
|
DAG.getConstant(0, T), Node->getOperand(2));
|
|
return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
|
|
cast<AtomicSDNode>(Node)->getMemoryVT(),
|
|
Node->getOperand(0),
|
|
Node->getOperand(1), negOp,
|
|
cast<AtomicSDNode>(Node)->getSrcValue(),
|
|
cast<AtomicSDNode>(Node)->getAlignment());
|
|
}
|
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
///
|
|
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
|
|
switch (Op.getOpcode()) {
|
|
default: assert(0 && "Should not custom lower this!");
|
|
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
|
|
case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
|
|
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
|
|
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
|
|
case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
|
|
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
|
|
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
|
|
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
|
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
|
|
case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
|
|
case ISD::SHL_PARTS:
|
|
case ISD::SRA_PARTS:
|
|
case ISD::SRL_PARTS: return LowerShift(Op, DAG);
|
|
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
|
|
case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
|
|
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
|
|
case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
|
|
case ISD::FABS: return LowerFABS(Op, DAG);
|
|
case ISD::FNEG: return LowerFNEG(Op, DAG);
|
|
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
|
|
case ISD::SETCC: return LowerSETCC(Op, DAG);
|
|
case ISD::VSETCC: return LowerVSETCC(Op, DAG);
|
|
case ISD::SELECT: return LowerSELECT(Op, DAG);
|
|
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
|
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
|
case ISD::CALL: return LowerCALL(Op, DAG);
|
|
case ISD::RET: return LowerRET(Op, DAG);
|
|
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
|
|
case ISD::VASTART: return LowerVASTART(Op, DAG);
|
|
case ISD::VAARG: return LowerVAARG(Op, DAG);
|
|
case ISD::VACOPY: return LowerVACOPY(Op, DAG);
|
|
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
|
|
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
|
|
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
|
|
case ISD::FRAME_TO_ARGS_OFFSET:
|
|
return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
|
|
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
|
|
case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
|
|
case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
|
|
case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
|
|
case ISD::CTLZ: return LowerCTLZ(Op, DAG);
|
|
case ISD::CTTZ: return LowerCTTZ(Op, DAG);
|
|
case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
|
|
case ISD::SADDO:
|
|
case ISD::UADDO:
|
|
case ISD::SSUBO:
|
|
case ISD::USUBO:
|
|
case ISD::SMULO:
|
|
case ISD::UMULO: return LowerXALUO(Op, DAG);
|
|
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
|
|
}
|
|
}
|
|
|
|
void X86TargetLowering::
|
|
ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
|
|
SelectionDAG &DAG, unsigned NewOp) {
|
|
MVT T = Node->getValueType(0);
|
|
DebugLoc dl = Node->getDebugLoc();
|
|
assert (T == MVT::i64 && "Only know how to expand i64 atomics");
|
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
SDValue In1 = Node->getOperand(1);
|
|
SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
|
|
Node->getOperand(2), DAG.getIntPtrConstant(0));
|
|
SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
|
|
Node->getOperand(2), DAG.getIntPtrConstant(1));
|
|
// This is a generalized SDNode, not an AtomicSDNode, so it doesn't
|
|
// have a MemOperand. Pass the info through as a normal operand.
|
|
SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
|
|
SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
|
|
SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
|
|
SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
|
|
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
|
|
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
|
|
Results.push_back(Result.getValue(2));
|
|
}
|
|
|
|
/// ReplaceNodeResults - Replace a node with an illegal result type
|
|
/// with a new node built out of custom code.
|
|
void X86TargetLowering::ReplaceNodeResults(SDNode *N,
|
|
SmallVectorImpl<SDValue>&Results,
|
|
SelectionDAG &DAG) {
|
|
DebugLoc dl = N->getDebugLoc();
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
assert(false && "Do not know how to custom type legalize this operation!");
|
|
return;
|
|
case ISD::FP_TO_SINT: {
|
|
std::pair<SDValue,SDValue> Vals =
|
|
FP_TO_INTHelper(SDValue(N, 0), DAG, true);
|
|
SDValue FIST = Vals.first, StackSlot = Vals.second;
|
|
if (FIST.getNode() != 0) {
|
|
MVT VT = N->getValueType(0);
|
|
// Return a load from the stack slot.
|
|
Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
|
|
}
|
|
return;
|
|
}
|
|
case ISD::READCYCLECOUNTER: {
|
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SDValue TheChain = N->getOperand(0);
|
|
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
|
|
SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
|
|
rd.getValue(1));
|
|
SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
|
|
eax.getValue(2));
|
|
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
|
|
SDValue Ops[] = { eax, edx };
|
|
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
|
|
Results.push_back(edx.getValue(1));
|
|
return;
|
|
}
|
|
case ISD::ATOMIC_CMP_SWAP: {
|
|
MVT T = N->getValueType(0);
|
|
assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
|
|
SDValue cpInL, cpInH;
|
|
cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
|
|
DAG.getConstant(0, MVT::i32));
|
|
cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
|
|
DAG.getConstant(1, MVT::i32));
|
|
cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
|
|
cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
|
|
cpInL.getValue(1));
|
|
SDValue swapInL, swapInH;
|
|
swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
|
|
DAG.getConstant(0, MVT::i32));
|
|
swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
|
|
DAG.getConstant(1, MVT::i32));
|
|
swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
|
|
cpInH.getValue(1));
|
|
swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
|
|
swapInL.getValue(1));
|
|
SDValue Ops[] = { swapInH.getValue(0),
|
|
N->getOperand(1),
|
|
swapInH.getValue(1) };
|
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
|
|
SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
|
|
MVT::i32, Result.getValue(1));
|
|
SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
|
|
MVT::i32, cpOutL.getValue(2));
|
|
SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
|
|
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
|
|
Results.push_back(cpOutH.getValue(1));
|
|
return;
|
|
}
|
|
case ISD::ATOMIC_LOAD_ADD:
|
|
ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
|
|
return;
|
|
case ISD::ATOMIC_LOAD_AND:
|
|
ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
|
|
return;
|
|
case ISD::ATOMIC_LOAD_NAND:
|
|
ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
|
|
return;
|
|
case ISD::ATOMIC_LOAD_OR:
|
|
ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
|
|
return;
|
|
case ISD::ATOMIC_LOAD_SUB:
|
|
ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
|
|
return;
|
|
case ISD::ATOMIC_LOAD_XOR:
|
|
ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
|
|
return;
|
|
case ISD::ATOMIC_SWAP:
|
|
ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
|
|
return;
|
|
}
|
|
}
|
|
|
|
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
default: return NULL;
|
|
case X86ISD::BSF: return "X86ISD::BSF";
|
|
case X86ISD::BSR: return "X86ISD::BSR";
|
|
case X86ISD::SHLD: return "X86ISD::SHLD";
|
|
case X86ISD::SHRD: return "X86ISD::SHRD";
|
|
case X86ISD::FAND: return "X86ISD::FAND";
|
|
case X86ISD::FOR: return "X86ISD::FOR";
|
|
case X86ISD::FXOR: return "X86ISD::FXOR";
|
|
case X86ISD::FSRL: return "X86ISD::FSRL";
|
|
case X86ISD::FILD: return "X86ISD::FILD";
|
|
case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
|
|
case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
|
|
case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
|
|
case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
|
|
case X86ISD::FLD: return "X86ISD::FLD";
|
|
case X86ISD::FST: return "X86ISD::FST";
|
|
case X86ISD::CALL: return "X86ISD::CALL";
|
|
case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
|
|
case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
|
|
case X86ISD::BT: return "X86ISD::BT";
|
|
case X86ISD::CMP: return "X86ISD::CMP";
|
|
case X86ISD::COMI: return "X86ISD::COMI";
|
|
case X86ISD::UCOMI: return "X86ISD::UCOMI";
|
|
case X86ISD::SETCC: return "X86ISD::SETCC";
|
|
case X86ISD::CMOV: return "X86ISD::CMOV";
|
|
case X86ISD::BRCOND: return "X86ISD::BRCOND";
|
|
case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
|
|
case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
|
|
case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
|
|
case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
|
|
case X86ISD::Wrapper: return "X86ISD::Wrapper";
|
|
case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
|
|
case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
|
|
case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
|
|
case X86ISD::PINSRB: return "X86ISD::PINSRB";
|
|
case X86ISD::PINSRW: return "X86ISD::PINSRW";
|
|
case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
|
|
case X86ISD::FMAX: return "X86ISD::FMAX";
|
|
case X86ISD::FMIN: return "X86ISD::FMIN";
|
|
case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
|
|
case X86ISD::FRCP: return "X86ISD::FRCP";
|
|
case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
|
|
case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
|
|
case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
|
|
case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
|
|
case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
|
|
case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
|
|
case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
|
|
case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
|
|
case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
|
|
case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
|
|
case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
|
|
case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
|
|
case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
|
|
case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
|
|
case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
|
|
case X86ISD::VSHL: return "X86ISD::VSHL";
|
|
case X86ISD::VSRL: return "X86ISD::VSRL";
|
|
case X86ISD::CMPPD: return "X86ISD::CMPPD";
|
|
case X86ISD::CMPPS: return "X86ISD::CMPPS";
|
|
case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
|
|
case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
|
|
case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
|
|
case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
|
|
case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
|
|
case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
|
|
case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
|
|
case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
|
|
case X86ISD::ADD: return "X86ISD::ADD";
|
|
case X86ISD::SUB: return "X86ISD::SUB";
|
|
case X86ISD::SMUL: return "X86ISD::SMUL";
|
|
case X86ISD::UMUL: return "X86ISD::UMUL";
|
|
case X86ISD::INC: return "X86ISD::INC";
|
|
case X86ISD::DEC: return "X86ISD::DEC";
|
|
case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
|
|
}
|
|
}
|
|
|
|
// isLegalAddressingMode - Return true if the addressing mode represented
|
|
// by AM is legal for this target, for a load/store of the specified type.
|
|
bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
|
|
const Type *Ty) const {
|
|
// X86 supports extremely general addressing modes.
|
|
|
|
// X86 allows a sign-extended 32-bit immediate field as a displacement.
|
|
if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
|
|
return false;
|
|
|
|
if (AM.BaseGV) {
|
|
// We can only fold this if we don't need an extra load.
|
|
if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
|
|
return false;
|
|
// If BaseGV requires a register, we cannot also have a BaseReg.
|
|
if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
|
|
AM.HasBaseReg)
|
|
return false;
|
|
|
|
// X86-64 only supports addr of globals in small code model.
|
|
if (Subtarget->is64Bit()) {
|
|
if (getTargetMachine().getCodeModel() != CodeModel::Small)
|
|
return false;
|
|
// If lower 4G is not available, then we must use rip-relative addressing.
|
|
if (AM.BaseOffs || AM.Scale > 1)
|
|
return false;
|
|
}
|
|
}
|
|
|
|
switch (AM.Scale) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
// These scales always work.
|
|
break;
|
|
case 3:
|
|
case 5:
|
|
case 9:
|
|
// These scales are formed with basereg+scalereg. Only accept if there is
|
|
// no basereg yet.
|
|
if (AM.HasBaseReg)
|
|
return false;
|
|
break;
|
|
default: // Other stuff never works.
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
|
|
if (!Ty1->isInteger() || !Ty2->isInteger())
|
|
return false;
|
|
unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
|
|
unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
|
|
if (NumBits1 <= NumBits2)
|
|
return false;
|
|
return Subtarget->is64Bit() || NumBits1 < 64;
|
|
}
|
|
|
|
bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
|
|
if (!VT1.isInteger() || !VT2.isInteger())
|
|
return false;
|
|
unsigned NumBits1 = VT1.getSizeInBits();
|
|
unsigned NumBits2 = VT2.getSizeInBits();
|
|
if (NumBits1 <= NumBits2)
|
|
return false;
|
|
return Subtarget->is64Bit() || NumBits1 < 64;
|
|
}
|
|
|
|
bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
|
|
// x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
|
|
return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
|
|
}
|
|
|
|
bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
|
|
// x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
|
|
return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
|
|
}
|
|
|
|
bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const {
|
|
// i16 instructions are longer (0x66 prefix) and potentially slower.
|
|
return !(VT1 == MVT::i32 && VT2 == MVT::i16);
|
|
}
|
|
|
|
/// isShuffleMaskLegal - Targets can use this to indicate that they only
|
|
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
|
|
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
|
|
/// are assumed to be legal.
|
|
bool
|
|
X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
|
|
MVT VT) const {
|
|
// Only do shuffles on 128-bit vector types for now.
|
|
if (VT.getSizeInBits() == 64)
|
|
return false;
|
|
|
|
// FIXME: pshufb, blends, palignr, shifts.
|
|
return (VT.getVectorNumElements() == 2 ||
|
|
ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
|
|
isMOVLMask(M, VT) ||
|
|
isSHUFPMask(M, VT) ||
|
|
isPSHUFDMask(M, VT) ||
|
|
isPSHUFHWMask(M, VT) ||
|
|
isPSHUFLWMask(M, VT) ||
|
|
isUNPCKLMask(M, VT) ||
|
|
isUNPCKHMask(M, VT) ||
|
|
isUNPCKL_v_undef_Mask(M, VT) ||
|
|
isUNPCKH_v_undef_Mask(M, VT));
|
|
}
|
|
|
|
bool
|
|
X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
MVT VT) const {
|
|
unsigned NumElts = VT.getVectorNumElements();
|
|
// FIXME: This collection of masks seems suspect.
|
|
if (NumElts == 2)
|
|
return true;
|
|
if (NumElts == 4 && VT.getSizeInBits() == 128) {
|
|
return (isMOVLMask(Mask, VT) ||
|
|
isCommutedMOVLMask(Mask, VT, true) ||
|
|
isSHUFPMask(Mask, VT) ||
|
|
isCommutedSHUFPMask(Mask, VT));
|
|
}
|
|
return false;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Scheduler Hooks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// private utility function
|
|
MachineBasicBlock *
|
|
X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
|
|
MachineBasicBlock *MBB,
|
|
unsigned regOpc,
|
|
unsigned immOpc,
|
|
unsigned LoadOpc,
|
|
unsigned CXchgOpc,
|
|
unsigned copyOpc,
|
|
unsigned notOpc,
|
|
unsigned EAXreg,
|
|
TargetRegisterClass *RC,
|
|
bool invSrc) const {
|
|
// For the atomic bitwise operator, we generate
|
|
// thisMBB:
|
|
// newMBB:
|
|
// ld t1 = [bitinstr.addr]
|
|
// op t2 = t1, [bitinstr.val]
|
|
// mov EAX = t1
|
|
// lcs dest = [bitinstr.addr], t2 [EAX is implicit]
|
|
// bz newMBB
|
|
// fallthrough -->nextMBB
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
|
|
MachineFunction::iterator MBBIter = MBB;
|
|
++MBBIter;
|
|
|
|
/// First build the CFG
|
|
MachineFunction *F = MBB->getParent();
|
|
MachineBasicBlock *thisMBB = MBB;
|
|
MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
F->insert(MBBIter, newMBB);
|
|
F->insert(MBBIter, nextMBB);
|
|
|
|
// Move all successors to thisMBB to nextMBB
|
|
nextMBB->transferSuccessors(thisMBB);
|
|
|
|
// Update thisMBB to fall through to newMBB
|
|
thisMBB->addSuccessor(newMBB);
|
|
|
|
// newMBB jumps to itself and fall through to nextMBB
|
|
newMBB->addSuccessor(nextMBB);
|
|
newMBB->addSuccessor(newMBB);
|
|
|
|
// Insert instructions into newMBB based on incoming instruction
|
|
assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
|
|
"unexpected number of operands");
|
|
DebugLoc dl = bInstr->getDebugLoc();
|
|
MachineOperand& destOper = bInstr->getOperand(0);
|
|
MachineOperand* argOpers[2 + X86AddrNumOperands];
|
|
int numArgs = bInstr->getNumOperands() - 1;
|
|
for (int i=0; i < numArgs; ++i)
|
|
argOpers[i] = &bInstr->getOperand(i+1);
|
|
|
|
// x86 address has 4 operands: base, index, scale, and displacement
|
|
int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
|
|
int valArgIndx = lastAddrIndx + 1;
|
|
|
|
unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
|
|
MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
|
|
for (int i=0; i <= lastAddrIndx; ++i)
|
|
(*MIB).addOperand(*argOpers[i]);
|
|
|
|
unsigned tt = F->getRegInfo().createVirtualRegister(RC);
|
|
if (invSrc) {
|
|
MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
|
|
}
|
|
else
|
|
tt = t1;
|
|
|
|
unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
|
|
assert((argOpers[valArgIndx]->isReg() ||
|
|
argOpers[valArgIndx]->isImm()) &&
|
|
"invalid operand");
|
|
if (argOpers[valArgIndx]->isReg())
|
|
MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
|
|
else
|
|
MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
|
|
MIB.addReg(tt);
|
|
(*MIB).addOperand(*argOpers[valArgIndx]);
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
|
|
MIB.addReg(t1);
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
|
|
for (int i=0; i <= lastAddrIndx; ++i)
|
|
(*MIB).addOperand(*argOpers[i]);
|
|
MIB.addReg(t2);
|
|
assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
|
|
(*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
|
|
MIB.addReg(EAXreg);
|
|
|
|
// insert branch
|
|
BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
|
|
|
|
F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
|
|
return nextMBB;
|
|
}
|
|
|
|
// private utility function: 64 bit atomics on 32 bit host.
|
|
MachineBasicBlock *
|
|
X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
|
|
MachineBasicBlock *MBB,
|
|
unsigned regOpcL,
|
|
unsigned regOpcH,
|
|
unsigned immOpcL,
|
|
unsigned immOpcH,
|
|
bool invSrc) const {
|
|
// For the atomic bitwise operator, we generate
|
|
// thisMBB (instructions are in pairs, except cmpxchg8b)
|
|
// ld t1,t2 = [bitinstr.addr]
|
|
// newMBB:
|
|
// out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
|
|
// op t5, t6 <- out1, out2, [bitinstr.val]
|
|
// (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
|
|
// mov ECX, EBX <- t5, t6
|
|
// mov EAX, EDX <- t1, t2
|
|
// cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
|
|
// mov t3, t4 <- EAX, EDX
|
|
// bz newMBB
|
|
// result in out1, out2
|
|
// fallthrough -->nextMBB
|
|
|
|
const TargetRegisterClass *RC = X86::GR32RegisterClass;
|
|
const unsigned LoadOpc = X86::MOV32rm;
|
|
const unsigned copyOpc = X86::MOV32rr;
|
|
const unsigned NotOpc = X86::NOT32r;
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
|
|
MachineFunction::iterator MBBIter = MBB;
|
|
++MBBIter;
|
|
|
|
/// First build the CFG
|
|
MachineFunction *F = MBB->getParent();
|
|
MachineBasicBlock *thisMBB = MBB;
|
|
MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
F->insert(MBBIter, newMBB);
|
|
F->insert(MBBIter, nextMBB);
|
|
|
|
// Move all successors to thisMBB to nextMBB
|
|
nextMBB->transferSuccessors(thisMBB);
|
|
|
|
// Update thisMBB to fall through to newMBB
|
|
thisMBB->addSuccessor(newMBB);
|
|
|
|
// newMBB jumps to itself and fall through to nextMBB
|
|
newMBB->addSuccessor(nextMBB);
|
|
newMBB->addSuccessor(newMBB);
|
|
|
|
DebugLoc dl = bInstr->getDebugLoc();
|
|
// Insert instructions into newMBB based on incoming instruction
|
|
// There are 8 "real" operands plus 9 implicit def/uses, ignored here.
|
|
assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
|
|
"unexpected number of operands");
|
|
MachineOperand& dest1Oper = bInstr->getOperand(0);
|
|
MachineOperand& dest2Oper = bInstr->getOperand(1);
|
|
MachineOperand* argOpers[2 + X86AddrNumOperands];
|
|
for (int i=0; i < 2 + X86AddrNumOperands; ++i)
|
|
argOpers[i] = &bInstr->getOperand(i+2);
|
|
|
|
// x86 address has 4 operands: base, index, scale, and displacement
|
|
int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
|
|
|
|
unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
|
|
MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
|
|
for (int i=0; i <= lastAddrIndx; ++i)
|
|
(*MIB).addOperand(*argOpers[i]);
|
|
unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
|
|
MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
|
|
// add 4 to displacement.
|
|
for (int i=0; i <= lastAddrIndx-2; ++i)
|
|
(*MIB).addOperand(*argOpers[i]);
|
|
MachineOperand newOp3 = *(argOpers[3]);
|
|
if (newOp3.isImm())
|
|
newOp3.setImm(newOp3.getImm()+4);
|
|
else
|
|
newOp3.setOffset(newOp3.getOffset()+4);
|
|
(*MIB).addOperand(newOp3);
|
|
(*MIB).addOperand(*argOpers[lastAddrIndx]);
|
|
|
|
// t3/4 are defined later, at the bottom of the loop
|
|
unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
|
|
unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
|
|
BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
|
|
.addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
|
|
BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
|
|
.addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
|
|
|
|
unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
|
|
unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
|
|
if (invSrc) {
|
|
MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
|
|
MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
|
|
} else {
|
|
tt1 = t1;
|
|
tt2 = t2;
|
|
}
|
|
|
|
int valArgIndx = lastAddrIndx + 1;
|
|
assert((argOpers[valArgIndx]->isReg() ||
|
|
argOpers[valArgIndx]->isImm()) &&
|
|
"invalid operand");
|
|
unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
|
|
unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
|
|
if (argOpers[valArgIndx]->isReg())
|
|
MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
|
|
else
|
|
MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
|
|
if (regOpcL != X86::MOV32rr)
|
|
MIB.addReg(tt1);
|
|
(*MIB).addOperand(*argOpers[valArgIndx]);
|
|
assert(argOpers[valArgIndx + 1]->isReg() ==
|
|
argOpers[valArgIndx]->isReg());
|
|
assert(argOpers[valArgIndx + 1]->isImm() ==
|
|
argOpers[valArgIndx]->isImm());
|
|
if (argOpers[valArgIndx + 1]->isReg())
|
|
MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
|
|
else
|
|
MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
|
|
if (regOpcH != X86::MOV32rr)
|
|
MIB.addReg(tt2);
|
|
(*MIB).addOperand(*argOpers[valArgIndx + 1]);
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
|
|
MIB.addReg(t1);
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
|
|
MIB.addReg(t2);
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
|
|
MIB.addReg(t5);
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
|
|
MIB.addReg(t6);
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
|
|
for (int i=0; i <= lastAddrIndx; ++i)
|
|
(*MIB).addOperand(*argOpers[i]);
|
|
|
|
assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
|
|
(*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
|
|
MIB.addReg(X86::EAX);
|
|
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
|
|
MIB.addReg(X86::EDX);
|
|
|
|
// insert branch
|
|
BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
|
|
|
|
F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
|
|
return nextMBB;
|
|
}
|
|
|
|
// private utility function
|
|
MachineBasicBlock *
|
|
X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
|
|
MachineBasicBlock *MBB,
|
|
unsigned cmovOpc) const {
|
|
// For the atomic min/max operator, we generate
|
|
// thisMBB:
|
|
// newMBB:
|
|
// ld t1 = [min/max.addr]
|
|
// mov t2 = [min/max.val]
|
|
// cmp t1, t2
|
|
// cmov[cond] t2 = t1
|
|
// mov EAX = t1
|
|
// lcs dest = [bitinstr.addr], t2 [EAX is implicit]
|
|
// bz newMBB
|
|
// fallthrough -->nextMBB
|
|
//
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
|
|
MachineFunction::iterator MBBIter = MBB;
|
|
++MBBIter;
|
|
|
|
/// First build the CFG
|
|
MachineFunction *F = MBB->getParent();
|
|
MachineBasicBlock *thisMBB = MBB;
|
|
MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
F->insert(MBBIter, newMBB);
|
|
F->insert(MBBIter, nextMBB);
|
|
|
|
// Move all successors to thisMBB to nextMBB
|
|
nextMBB->transferSuccessors(thisMBB);
|
|
|
|
// Update thisMBB to fall through to newMBB
|
|
thisMBB->addSuccessor(newMBB);
|
|
|
|
// newMBB jumps to newMBB and fall through to nextMBB
|
|
newMBB->addSuccessor(nextMBB);
|
|
newMBB->addSuccessor(newMBB);
|
|
|
|
DebugLoc dl = mInstr->getDebugLoc();
|
|
// Insert instructions into newMBB based on incoming instruction
|
|
assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
|
|
"unexpected number of operands");
|
|
MachineOperand& destOper = mInstr->getOperand(0);
|
|
MachineOperand* argOpers[2 + X86AddrNumOperands];
|
|
int numArgs = mInstr->getNumOperands() - 1;
|
|
for (int i=0; i < numArgs; ++i)
|
|
argOpers[i] = &mInstr->getOperand(i+1);
|
|
|
|
// x86 address has 4 operands: base, index, scale, and displacement
|
|
int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
|
|
int valArgIndx = lastAddrIndx + 1;
|
|
|
|
unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
|
|
MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
|
|
for (int i=0; i <= lastAddrIndx; ++i)
|
|
(*MIB).addOperand(*argOpers[i]);
|
|
|
|
// We only support register and immediate values
|
|
assert((argOpers[valArgIndx]->isReg() ||
|
|
argOpers[valArgIndx]->isImm()) &&
|
|
"invalid operand");
|
|
|
|
unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
|
|
if (argOpers[valArgIndx]->isReg())
|
|
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
|
|
else
|
|
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
|
|
(*MIB).addOperand(*argOpers[valArgIndx]);
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
|
|
MIB.addReg(t1);
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
|
|
MIB.addReg(t1);
|
|
MIB.addReg(t2);
|
|
|
|
// Generate movc
|
|
unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
|
|
MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
|
|
MIB.addReg(t2);
|
|
MIB.addReg(t1);
|
|
|
|
// Cmp and exchange if none has modified the memory location
|
|
MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
|
|
for (int i=0; i <= lastAddrIndx; ++i)
|
|
(*MIB).addOperand(*argOpers[i]);
|
|
MIB.addReg(t3);
|
|
assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
|
|
(*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
|
|
|
|
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
|
|
MIB.addReg(X86::EAX);
|
|
|
|
// insert branch
|
|
BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
|
|
|
|
F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
|
|
return nextMBB;
|
|
}
|
|
|
|
|
|
MachineBasicBlock *
|
|
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB) const {
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
switch (MI->getOpcode()) {
|
|
default: assert(false && "Unexpected instr type to insert");
|
|
case X86::CMOV_V1I64:
|
|
case X86::CMOV_FR32:
|
|
case X86::CMOV_FR64:
|
|
case X86::CMOV_V4F32:
|
|
case X86::CMOV_V2F64:
|
|
case X86::CMOV_V2I64: {
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
// true/false values to select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator It = BB;
|
|
++It;
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// cmpTY ccX, r1, r2
|
|
// bCC copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
unsigned Opc =
|
|
X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
|
|
BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
|
|
F->insert(It, copy0MBB);
|
|
F->insert(It, sinkMBB);
|
|
// Update machine-CFG edges by transferring all successors of the current
|
|
// block to the new block which will contain the Phi node for the select.
|
|
sinkMBB->transferSuccessors(BB);
|
|
|
|
// Add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
|
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
case X86::FP32_TO_INT16_IN_MEM:
|
|
case X86::FP32_TO_INT32_IN_MEM:
|
|
case X86::FP32_TO_INT64_IN_MEM:
|
|
case X86::FP64_TO_INT16_IN_MEM:
|
|
case X86::FP64_TO_INT32_IN_MEM:
|
|
case X86::FP64_TO_INT64_IN_MEM:
|
|
case X86::FP80_TO_INT16_IN_MEM:
|
|
case X86::FP80_TO_INT32_IN_MEM:
|
|
case X86::FP80_TO_INT64_IN_MEM: {
|
|
// Change the floating point control register to use "round towards zero"
|
|
// mode when truncating to an integer value.
|
|
MachineFunction *F = BB->getParent();
|
|
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
|
|
addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
|
|
|
|
// Load the old value of the high byte of the control word...
|
|
unsigned OldCW =
|
|
F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
|
|
addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
|
|
CWFrameIdx);
|
|
|
|
// Set the high part to be round to zero...
|
|
addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
|
|
.addImm(0xC7F);
|
|
|
|
// Reload the modified control word now...
|
|
addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
|
|
|
|
// Restore the memory image of control word to original value
|
|
addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
|
|
.addReg(OldCW);
|
|
|
|
// Get the X86 opcode to use.
|
|
unsigned Opc;
|
|
switch (MI->getOpcode()) {
|
|
default: assert(0 && "illegal opcode!");
|
|
case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
|
|
case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
|
|
case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
|
|
case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
|
|
case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
|
|
case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
|
|
case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
|
|
case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
|
|
case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
|
|
}
|
|
|
|
X86AddressMode AM;
|
|
MachineOperand &Op = MI->getOperand(0);
|
|
if (Op.isReg()) {
|
|
AM.BaseType = X86AddressMode::RegBase;
|
|
AM.Base.Reg = Op.getReg();
|
|
} else {
|
|
AM.BaseType = X86AddressMode::FrameIndexBase;
|
|
AM.Base.FrameIndex = Op.getIndex();
|
|
}
|
|
Op = MI->getOperand(1);
|
|
if (Op.isImm())
|
|
AM.Scale = Op.getImm();
|
|
Op = MI->getOperand(2);
|
|
if (Op.isImm())
|
|
AM.IndexReg = Op.getImm();
|
|
Op = MI->getOperand(3);
|
|
if (Op.isGlobal()) {
|
|
AM.GV = Op.getGlobal();
|
|
} else {
|
|
AM.Disp = Op.getImm();
|
|
}
|
|
addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
|
|
.addReg(MI->getOperand(X86AddrNumOperands).getReg());
|
|
|
|
// Reload the original control word now.
|
|
addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
|
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
case X86::ATOMAND32:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
|
|
X86::AND32ri, X86::MOV32rm,
|
|
X86::LCMPXCHG32, X86::MOV32rr,
|
|
X86::NOT32r, X86::EAX,
|
|
X86::GR32RegisterClass);
|
|
case X86::ATOMOR32:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
|
|
X86::OR32ri, X86::MOV32rm,
|
|
X86::LCMPXCHG32, X86::MOV32rr,
|
|
X86::NOT32r, X86::EAX,
|
|
X86::GR32RegisterClass);
|
|
case X86::ATOMXOR32:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
|
|
X86::XOR32ri, X86::MOV32rm,
|
|
X86::LCMPXCHG32, X86::MOV32rr,
|
|
X86::NOT32r, X86::EAX,
|
|
X86::GR32RegisterClass);
|
|
case X86::ATOMNAND32:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
|
|
X86::AND32ri, X86::MOV32rm,
|
|
X86::LCMPXCHG32, X86::MOV32rr,
|
|
X86::NOT32r, X86::EAX,
|
|
X86::GR32RegisterClass, true);
|
|
case X86::ATOMMIN32:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
|
|
case X86::ATOMMAX32:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
|
|
case X86::ATOMUMIN32:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
|
|
case X86::ATOMUMAX32:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
|
|
|
|
case X86::ATOMAND16:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
|
|
X86::AND16ri, X86::MOV16rm,
|
|
X86::LCMPXCHG16, X86::MOV16rr,
|
|
X86::NOT16r, X86::AX,
|
|
X86::GR16RegisterClass);
|
|
case X86::ATOMOR16:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
|
|
X86::OR16ri, X86::MOV16rm,
|
|
X86::LCMPXCHG16, X86::MOV16rr,
|
|
X86::NOT16r, X86::AX,
|
|
X86::GR16RegisterClass);
|
|
case X86::ATOMXOR16:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
|
|
X86::XOR16ri, X86::MOV16rm,
|
|
X86::LCMPXCHG16, X86::MOV16rr,
|
|
X86::NOT16r, X86::AX,
|
|
X86::GR16RegisterClass);
|
|
case X86::ATOMNAND16:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
|
|
X86::AND16ri, X86::MOV16rm,
|
|
X86::LCMPXCHG16, X86::MOV16rr,
|
|
X86::NOT16r, X86::AX,
|
|
X86::GR16RegisterClass, true);
|
|
case X86::ATOMMIN16:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
|
|
case X86::ATOMMAX16:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
|
|
case X86::ATOMUMIN16:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
|
|
case X86::ATOMUMAX16:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
|
|
|
|
case X86::ATOMAND8:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
|
|
X86::AND8ri, X86::MOV8rm,
|
|
X86::LCMPXCHG8, X86::MOV8rr,
|
|
X86::NOT8r, X86::AL,
|
|
X86::GR8RegisterClass);
|
|
case X86::ATOMOR8:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
|
|
X86::OR8ri, X86::MOV8rm,
|
|
X86::LCMPXCHG8, X86::MOV8rr,
|
|
X86::NOT8r, X86::AL,
|
|
X86::GR8RegisterClass);
|
|
case X86::ATOMXOR8:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
|
|
X86::XOR8ri, X86::MOV8rm,
|
|
X86::LCMPXCHG8, X86::MOV8rr,
|
|
X86::NOT8r, X86::AL,
|
|
X86::GR8RegisterClass);
|
|
case X86::ATOMNAND8:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
|
|
X86::AND8ri, X86::MOV8rm,
|
|
X86::LCMPXCHG8, X86::MOV8rr,
|
|
X86::NOT8r, X86::AL,
|
|
X86::GR8RegisterClass, true);
|
|
// FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
|
|
// This group is for 64-bit host.
|
|
case X86::ATOMAND64:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
|
|
X86::AND64ri32, X86::MOV64rm,
|
|
X86::LCMPXCHG64, X86::MOV64rr,
|
|
X86::NOT64r, X86::RAX,
|
|
X86::GR64RegisterClass);
|
|
case X86::ATOMOR64:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
|
|
X86::OR64ri32, X86::MOV64rm,
|
|
X86::LCMPXCHG64, X86::MOV64rr,
|
|
X86::NOT64r, X86::RAX,
|
|
X86::GR64RegisterClass);
|
|
case X86::ATOMXOR64:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
|
|
X86::XOR64ri32, X86::MOV64rm,
|
|
X86::LCMPXCHG64, X86::MOV64rr,
|
|
X86::NOT64r, X86::RAX,
|
|
X86::GR64RegisterClass);
|
|
case X86::ATOMNAND64:
|
|
return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
|
|
X86::AND64ri32, X86::MOV64rm,
|
|
X86::LCMPXCHG64, X86::MOV64rr,
|
|
X86::NOT64r, X86::RAX,
|
|
X86::GR64RegisterClass, true);
|
|
case X86::ATOMMIN64:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
|
|
case X86::ATOMMAX64:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
|
|
case X86::ATOMUMIN64:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
|
|
case X86::ATOMUMAX64:
|
|
return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
|
|
|
|
// This group does 64-bit operations on a 32-bit host.
|
|
case X86::ATOMAND6432:
|
|
return EmitAtomicBit6432WithCustomInserter(MI, BB,
|
|
X86::AND32rr, X86::AND32rr,
|
|
X86::AND32ri, X86::AND32ri,
|
|
false);
|
|
case X86::ATOMOR6432:
|
|
return EmitAtomicBit6432WithCustomInserter(MI, BB,
|
|
X86::OR32rr, X86::OR32rr,
|
|
X86::OR32ri, X86::OR32ri,
|
|
false);
|
|
case X86::ATOMXOR6432:
|
|
return EmitAtomicBit6432WithCustomInserter(MI, BB,
|
|
X86::XOR32rr, X86::XOR32rr,
|
|
X86::XOR32ri, X86::XOR32ri,
|
|
false);
|
|
case X86::ATOMNAND6432:
|
|
return EmitAtomicBit6432WithCustomInserter(MI, BB,
|
|
X86::AND32rr, X86::AND32rr,
|
|
X86::AND32ri, X86::AND32ri,
|
|
true);
|
|
case X86::ATOMADD6432:
|
|
return EmitAtomicBit6432WithCustomInserter(MI, BB,
|
|
X86::ADD32rr, X86::ADC32rr,
|
|
X86::ADD32ri, X86::ADC32ri,
|
|
false);
|
|
case X86::ATOMSUB6432:
|
|
return EmitAtomicBit6432WithCustomInserter(MI, BB,
|
|
X86::SUB32rr, X86::SBB32rr,
|
|
X86::SUB32ri, X86::SBB32ri,
|
|
false);
|
|
case X86::ATOMSWAP6432:
|
|
return EmitAtomicBit6432WithCustomInserter(MI, BB,
|
|
X86::MOV32rr, X86::MOV32rr,
|
|
X86::MOV32ri, X86::MOV32ri,
|
|
false);
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Optimization Hooks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
|
|
const APInt &Mask,
|
|
APInt &KnownZero,
|
|
APInt &KnownOne,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth) const {
|
|
unsigned Opc = Op.getOpcode();
|
|
assert((Opc >= ISD::BUILTIN_OP_END ||
|
|
Opc == ISD::INTRINSIC_WO_CHAIN ||
|
|
Opc == ISD::INTRINSIC_W_CHAIN ||
|
|
Opc == ISD::INTRINSIC_VOID) &&
|
|
"Should use MaskedValueIsZero if you don't know whether Op"
|
|
" is a target node!");
|
|
|
|
KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
|
|
switch (Opc) {
|
|
default: break;
|
|
case X86ISD::ADD:
|
|
case X86ISD::SUB:
|
|
case X86ISD::SMUL:
|
|
case X86ISD::UMUL:
|
|
case X86ISD::INC:
|
|
case X86ISD::DEC:
|
|
// These nodes' second result is a boolean.
|
|
if (Op.getResNo() == 0)
|
|
break;
|
|
// Fallthrough
|
|
case X86ISD::SETCC:
|
|
KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
|
|
Mask.getBitWidth() - 1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
|
|
/// node is a GlobalAddress + offset.
|
|
bool X86TargetLowering::isGAPlusOffset(SDNode *N,
|
|
GlobalValue* &GA, int64_t &Offset) const{
|
|
if (N->getOpcode() == X86ISD::Wrapper) {
|
|
if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
|
|
GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
|
|
Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
|
|
return true;
|
|
}
|
|
}
|
|
return TargetLowering::isGAPlusOffset(N, GA, Offset);
|
|
}
|
|
|
|
static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
|
|
const TargetLowering &TLI) {
|
|
GlobalValue *GV;
|
|
int64_t Offset = 0;
|
|
if (TLI.isGAPlusOffset(Base, GV, Offset))
|
|
return (GV->getAlignment() >= N && (Offset % N) == 0);
|
|
// DAG combine handles the stack object case.
|
|
return false;
|
|
}
|
|
|
|
static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
|
|
MVT EVT, SDNode *&Base,
|
|
SelectionDAG &DAG, MachineFrameInfo *MFI,
|
|
const TargetLowering &TLI) {
|
|
Base = NULL;
|
|
for (unsigned i = 0; i < NumElems; ++i) {
|
|
if (N->getMaskElt(i) < 0) {
|
|
if (!Base)
|
|
return false;
|
|
continue;
|
|
}
|
|
|
|
SDValue Elt = DAG.getShuffleScalarElt(N, i);
|
|
if (!Elt.getNode() ||
|
|
(Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
|
|
return false;
|
|
if (!Base) {
|
|
Base = Elt.getNode();
|
|
if (Base->getOpcode() == ISD::UNDEF)
|
|
return false;
|
|
continue;
|
|
}
|
|
if (Elt.getOpcode() == ISD::UNDEF)
|
|
continue;
|
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(Elt);
|
|
LoadSDNode *LDBase = cast<LoadSDNode>(Base);
|
|
if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
|
|
/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
|
|
/// if the load addresses are consecutive, non-overlapping, and in the right
|
|
/// order. In the case of v2i64, it will see if it can rewrite the
|
|
/// shuffle to be an appropriate build vector so it can take advantage of
|
|
// performBuildVectorCombine.
|
|
static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
|
|
const TargetLowering &TLI) {
|
|
DebugLoc dl = N->getDebugLoc();
|
|
MVT VT = N->getValueType(0);
|
|
MVT EVT = VT.getVectorElementType();
|
|
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
|
|
unsigned NumElems = VT.getVectorNumElements();
|
|
|
|
// For x86-32 machines, if we see an insert and then a shuffle in a v2i64
|
|
// where the upper half is 0, it is advantageous to rewrite it as a build
|
|
// vector of (0, val) so it can use movq.
|
|
if (VT == MVT::v2i64) {
|
|
SDValue In[2];
|
|
In[0] = N->getOperand(0);
|
|
In[1] = N->getOperand(1);
|
|
int Idx0 = SVN->getMaskElt(0);
|
|
int Idx1 = SVN->getMaskElt(1);
|
|
// FIXME: can we take advantage of undef index?
|
|
if (Idx0 >= 0 && Idx1 >= 0 &&
|
|
In[Idx0/2].getOpcode() == ISD::INSERT_VECTOR_ELT &&
|
|
In[Idx1/2].getOpcode() == ISD::BUILD_VECTOR) {
|
|
ConstantSDNode* InsertVecIdx =
|
|
dyn_cast<ConstantSDNode>(In[Idx0/2].getOperand(2));
|
|
if (InsertVecIdx &&
|
|
InsertVecIdx->getZExtValue() == (unsigned)(Idx0 % 2) &&
|
|
isZeroNode(In[Idx1/2].getOperand(Idx1 % 2))) {
|
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
|
|
In[Idx0/2].getOperand(1),
|
|
In[Idx1/2].getOperand(Idx1 % 2));
|
|
}
|
|
}
|
|
}
|
|
|
|
// Try to combine a vector_shuffle into a 128-bit load.
|
|
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
|
SDNode *Base = NULL;
|
|
if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, Base, DAG, MFI, TLI))
|
|
return SDValue();
|
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(Base);
|
|
if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
|
|
return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
|
|
LD->getSrcValue(), LD->getSrcValueOffset(),
|
|
LD->isVolatile());
|
|
return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
|
|
LD->getSrcValue(), LD->getSrcValueOffset(),
|
|
LD->isVolatile(), LD->getAlignment());
|
|
}
|
|
|
|
/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
|
|
static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
const X86Subtarget *Subtarget,
|
|
const TargetLowering &TLI) {
|
|
unsigned NumOps = N->getNumOperands();
|
|
DebugLoc dl = N->getDebugLoc();
|
|
|
|
// Ignore single operand BUILD_VECTOR.
|
|
if (NumOps == 1)
|
|
return SDValue();
|
|
|
|
MVT VT = N->getValueType(0);
|
|
MVT EVT = VT.getVectorElementType();
|
|
|
|
// Before or during type legalization, we want to try and convert a
|
|
// build_vector of an i64 load and a zero value into vzext_movl before the
|
|
// legalizer can break it up.
|
|
// FIXME: does the case below remove the need to do this?
|
|
if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) {
|
|
if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
|
|
return SDValue();
|
|
|
|
// This must be an insertion into a zero vector.
|
|
SDValue HighElt = N->getOperand(1);
|
|
if (!isZeroNode(HighElt))
|
|
return SDValue();
|
|
|
|
// Value must be a load.
|
|
SDNode *Base = N->getOperand(0).getNode();
|
|
if (!isa<LoadSDNode>(Base)) {
|
|
if (Base->getOpcode() != ISD::BIT_CONVERT)
|
|
return SDValue();
|
|
Base = Base->getOperand(0).getNode();
|
|
if (!isa<LoadSDNode>(Base))
|
|
return SDValue();
|
|
}
|
|
|
|
// Transform it into VZEXT_LOAD addr.
|
|
LoadSDNode *LD = cast<LoadSDNode>(Base);
|
|
|
|
// Load must not be an extload.
|
|
if (LD->getExtensionType() != ISD::NON_EXTLOAD)
|
|
return SDValue();
|
|
|
|
// Load type should legal type so we don't have to legalize it.
|
|
if (!TLI.isTypeLegal(VT))
|
|
return SDValue();
|
|
|
|
SDVTList Tys = DAG.getVTList(VT, MVT::Other);
|
|
SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
|
|
SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
|
|
TargetLowering::TargetLoweringOpt TLO(DAG);
|
|
TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
|
|
DCI.CommitTargetLoweringOpt(TLO);
|
|
return ResNode;
|
|
}
|
|
|
|
// The type legalizer will have broken apart v2i64 build_vector created during
|
|
// widening before the code which handles that case is run. Look for build
|
|
// vector (load, load + 4, 0/undef, 0/undef)
|
|
if (VT == MVT::v4i32 || VT == MVT::v4f32) {
|
|
LoadSDNode *LD0 = dyn_cast<LoadSDNode>(N->getOperand(0));
|
|
LoadSDNode *LD1 = dyn_cast<LoadSDNode>(N->getOperand(1));
|
|
if (!LD0 || !LD1)
|
|
return SDValue();
|
|
if (LD0->getExtensionType() != ISD::NON_EXTLOAD ||
|
|
LD1->getExtensionType() != ISD::NON_EXTLOAD)
|
|
return SDValue();
|
|
// Make sure the second elt is a consecutive load.
|
|
if (!TLI.isConsecutiveLoad(LD1, LD0, EVT.getSizeInBits()/8, 1,
|
|
DAG.getMachineFunction().getFrameInfo()))
|
|
return SDValue();
|
|
|
|
SDValue N2 = N->getOperand(2);
|
|
SDValue N3 = N->getOperand(3);
|
|
if (!isZeroNode(N2) && N2.getOpcode() != ISD::UNDEF)
|
|
return SDValue();
|
|
if (!isZeroNode(N3) && N3.getOpcode() != ISD::UNDEF)
|
|
return SDValue();
|
|
|
|
SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
|
|
SDValue Ops[] = { LD0->getChain(), LD0->getBasePtr() };
|
|
SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
|
|
TargetLowering::TargetLoweringOpt TLO(DAG);
|
|
TLO.CombineTo(SDValue(LD0, 1), ResNode.getValue(1));
|
|
DCI.CommitTargetLoweringOpt(TLO);
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
|
|
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
|
|
const X86Subtarget *Subtarget) {
|
|
DebugLoc DL = N->getDebugLoc();
|
|
SDValue Cond = N->getOperand(0);
|
|
// Get the LHS/RHS of the select.
|
|
SDValue LHS = N->getOperand(1);
|
|
SDValue RHS = N->getOperand(2);
|
|
|
|
// If we have SSE[12] support, try to form min/max nodes.
|
|
if (Subtarget->hasSSE2() &&
|
|
(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
|
|
Cond.getOpcode() == ISD::SETCC) {
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
|
|
|
|
unsigned Opcode = 0;
|
|
if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
|
|
switch (CC) {
|
|
default: break;
|
|
case ISD::SETOLE: // (X <= Y) ? X : Y -> min
|
|
case ISD::SETULE:
|
|
case ISD::SETLE:
|
|
if (!UnsafeFPMath) break;
|
|
// FALL THROUGH.
|
|
case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
|
|
case ISD::SETLT:
|
|
Opcode = X86ISD::FMIN;
|
|
break;
|
|
|
|
case ISD::SETOGT: // (X > Y) ? X : Y -> max
|
|
case ISD::SETUGT:
|
|
case ISD::SETGT:
|
|
if (!UnsafeFPMath) break;
|
|
// FALL THROUGH.
|
|
case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
|
|
case ISD::SETGE:
|
|
Opcode = X86ISD::FMAX;
|
|
break;
|
|
}
|
|
} else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
|
|
switch (CC) {
|
|
default: break;
|
|
case ISD::SETOGT: // (X > Y) ? Y : X -> min
|
|
case ISD::SETUGT:
|
|
case ISD::SETGT:
|
|
if (!UnsafeFPMath) break;
|
|
// FALL THROUGH.
|
|
case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
|
|
case ISD::SETGE:
|
|
Opcode = X86ISD::FMIN;
|
|
break;
|
|
|
|
case ISD::SETOLE: // (X <= Y) ? Y : X -> max
|
|
case ISD::SETULE:
|
|
case ISD::SETLE:
|
|
if (!UnsafeFPMath) break;
|
|
// FALL THROUGH.
|
|
case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
|
|
case ISD::SETLT:
|
|
Opcode = X86ISD::FMAX;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (Opcode)
|
|
return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
|
|
}
|
|
|
|
// If this is a select between two integer constants, try to do some
|
|
// optimizations.
|
|
if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
|
|
if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
|
|
// Don't do this for crazy integer types.
|
|
if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
|
|
// If this is efficiently invertible, canonicalize the LHSC/RHSC values
|
|
// so that TrueC (the true value) is larger than FalseC.
|
|
bool NeedsCondInvert = false;
|
|
|
|
if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
|
|
// Efficiently invertible.
|
|
(Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
|
|
(Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
|
|
isa<ConstantSDNode>(Cond.getOperand(1))))) {
|
|
NeedsCondInvert = true;
|
|
std::swap(TrueC, FalseC);
|
|
}
|
|
|
|
// Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
|
|
if (FalseC->getAPIntValue() == 0 &&
|
|
TrueC->getAPIntValue().isPowerOf2()) {
|
|
if (NeedsCondInvert) // Invert the condition if needed.
|
|
Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
|
|
DAG.getConstant(1, Cond.getValueType()));
|
|
|
|
// Zero extend the condition if needed.
|
|
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
|
|
|
|
unsigned ShAmt = TrueC->getAPIntValue().logBase2();
|
|
return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
|
|
DAG.getConstant(ShAmt, MVT::i8));
|
|
}
|
|
|
|
// Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
|
|
if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
|
|
if (NeedsCondInvert) // Invert the condition if needed.
|
|
Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
|
|
DAG.getConstant(1, Cond.getValueType()));
|
|
|
|
// Zero extend the condition if needed.
|
|
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
|
|
FalseC->getValueType(0), Cond);
|
|
return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
|
|
SDValue(FalseC, 0));
|
|
}
|
|
|
|
// Optimize cases that will turn into an LEA instruction. This requires
|
|
// an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
|
|
if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
|
|
uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
|
|
if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
|
|
|
|
bool isFastMultiplier = false;
|
|
if (Diff < 10) {
|
|
switch ((unsigned char)Diff) {
|
|
default: break;
|
|
case 1: // result = add base, cond
|
|
case 2: // result = lea base( , cond*2)
|
|
case 3: // result = lea base(cond, cond*2)
|
|
case 4: // result = lea base( , cond*4)
|
|
case 5: // result = lea base(cond, cond*4)
|
|
case 8: // result = lea base( , cond*8)
|
|
case 9: // result = lea base(cond, cond*8)
|
|
isFastMultiplier = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (isFastMultiplier) {
|
|
APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
|
|
if (NeedsCondInvert) // Invert the condition if needed.
|
|
Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
|
|
DAG.getConstant(1, Cond.getValueType()));
|
|
|
|
// Zero extend the condition if needed.
|
|
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
|
|
Cond);
|
|
// Scale the condition by the difference.
|
|
if (Diff != 1)
|
|
Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
|
|
DAG.getConstant(Diff, Cond.getValueType()));
|
|
|
|
// Add the base if non-zero.
|
|
if (FalseC->getAPIntValue() != 0)
|
|
Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
|
|
SDValue(FalseC, 0));
|
|
return Cond;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
|
|
static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
|
|
TargetLowering::DAGCombinerInfo &DCI) {
|
|
DebugLoc DL = N->getDebugLoc();
|
|
|
|
// If the flag operand isn't dead, don't touch this CMOV.
|
|
if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
|
|
return SDValue();
|
|
|
|
// If this is a select between two integer constants, try to do some
|
|
// optimizations. Note that the operands are ordered the opposite of SELECT
|
|
// operands.
|
|
if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
|
|
if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
|
|
// Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
|
|
// larger than FalseC (the false value).
|
|
X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
|
|
|
|
if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
|
|
CC = X86::GetOppositeBranchCondition(CC);
|
|
std::swap(TrueC, FalseC);
|
|
}
|
|
|
|
// Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
|
|
// This is efficient for any integer data type (including i8/i16) and
|
|
// shift amount.
|
|
if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
|
|
SDValue Cond = N->getOperand(3);
|
|
Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
|
|
DAG.getConstant(CC, MVT::i8), Cond);
|
|
|
|
// Zero extend the condition if needed.
|
|
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
|
|
|
|
unsigned ShAmt = TrueC->getAPIntValue().logBase2();
|
|
Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
|
|
DAG.getConstant(ShAmt, MVT::i8));
|
|
if (N->getNumValues() == 2) // Dead flag value?
|
|
return DCI.CombineTo(N, Cond, SDValue());
|
|
return Cond;
|
|
}
|
|
|
|
// Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
|
|
// for any integer data type, including i8/i16.
|
|
if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
|
|
SDValue Cond = N->getOperand(3);
|
|
Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
|
|
DAG.getConstant(CC, MVT::i8), Cond);
|
|
|
|
// Zero extend the condition if needed.
|
|
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
|
|
FalseC->getValueType(0), Cond);
|
|
Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
|
|
SDValue(FalseC, 0));
|
|
|
|
if (N->getNumValues() == 2) // Dead flag value?
|
|
return DCI.CombineTo(N, Cond, SDValue());
|
|
return Cond;
|
|
}
|
|
|
|
// Optimize cases that will turn into an LEA instruction. This requires
|
|
// an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
|
|
if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
|
|
uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
|
|
if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
|
|
|
|
bool isFastMultiplier = false;
|
|
if (Diff < 10) {
|
|
switch ((unsigned char)Diff) {
|
|
default: break;
|
|
case 1: // result = add base, cond
|
|
case 2: // result = lea base( , cond*2)
|
|
case 3: // result = lea base(cond, cond*2)
|
|
case 4: // result = lea base( , cond*4)
|
|
case 5: // result = lea base(cond, cond*4)
|
|
case 8: // result = lea base( , cond*8)
|
|
case 9: // result = lea base(cond, cond*8)
|
|
isFastMultiplier = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (isFastMultiplier) {
|
|
APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
|
|
SDValue Cond = N->getOperand(3);
|
|
Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
|
|
DAG.getConstant(CC, MVT::i8), Cond);
|
|
// Zero extend the condition if needed.
|
|
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
|
|
Cond);
|
|
// Scale the condition by the difference.
|
|
if (Diff != 1)
|
|
Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
|
|
DAG.getConstant(Diff, Cond.getValueType()));
|
|
|
|
// Add the base if non-zero.
|
|
if (FalseC->getAPIntValue() != 0)
|
|
Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
|
|
SDValue(FalseC, 0));
|
|
if (N->getNumValues() == 2) // Dead flag value?
|
|
return DCI.CombineTo(N, Cond, SDValue());
|
|
return Cond;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
|
|
/// PerformMulCombine - Optimize a single multiply with constant into two
|
|
/// in order to implement it with two cheaper instructions, e.g.
|
|
/// LEA + SHL, LEA + LEA.
|
|
static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
|
|
TargetLowering::DAGCombinerInfo &DCI) {
|
|
if (DAG.getMachineFunction().
|
|
getFunction()->hasFnAttr(Attribute::OptimizeForSize))
|
|
return SDValue();
|
|
|
|
if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
|
|
return SDValue();
|
|
|
|
MVT VT = N->getValueType(0);
|
|
if (VT != MVT::i64)
|
|
return SDValue();
|
|
|
|
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
|
|
if (!C)
|
|
return SDValue();
|
|
uint64_t MulAmt = C->getZExtValue();
|
|
if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
|
|
return SDValue();
|
|
|
|
uint64_t MulAmt1 = 0;
|
|
uint64_t MulAmt2 = 0;
|
|
if ((MulAmt % 9) == 0) {
|
|
MulAmt1 = 9;
|
|
MulAmt2 = MulAmt / 9;
|
|
} else if ((MulAmt % 5) == 0) {
|
|
MulAmt1 = 5;
|
|
MulAmt2 = MulAmt / 5;
|
|
} else if ((MulAmt % 3) == 0) {
|
|
MulAmt1 = 3;
|
|
MulAmt2 = MulAmt / 3;
|
|
}
|
|
if (MulAmt2 &&
|
|
(isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
|
|
DebugLoc DL = N->getDebugLoc();
|
|
|
|
if (isPowerOf2_64(MulAmt2) &&
|
|
!(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
|
|
// If second multiplifer is pow2, issue it first. We want the multiply by
|
|
// 3, 5, or 9 to be folded into the addressing mode unless the lone use
|
|
// is an add.
|
|
std::swap(MulAmt1, MulAmt2);
|
|
|
|
SDValue NewMul;
|
|
if (isPowerOf2_64(MulAmt1))
|
|
NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
|
|
DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
|
|
else
|
|
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
|
|
DAG.getConstant(MulAmt1, VT));
|
|
|
|
if (isPowerOf2_64(MulAmt2))
|
|
NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
|
|
DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
|
|
else
|
|
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
|
|
DAG.getConstant(MulAmt2, VT));
|
|
|
|
// Do not add new nodes to DAG combiner worklist.
|
|
DCI.CombineTo(N, NewMul, false);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
|
|
/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
|
|
/// when possible.
|
|
static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
|
|
const X86Subtarget *Subtarget) {
|
|
// On X86 with SSE2 support, we can transform this to a vector shift if
|
|
// all elements are shifted by the same amount. We can't do this in legalize
|
|
// because the a constant vector is typically transformed to a constant pool
|
|
// so we have no knowledge of the shift amount.
|
|
if (!Subtarget->hasSSE2())
|
|
return SDValue();
|
|
|
|
MVT VT = N->getValueType(0);
|
|
if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
|
|
return SDValue();
|
|
|
|
SDValue ShAmtOp = N->getOperand(1);
|
|
MVT EltVT = VT.getVectorElementType();
|
|
DebugLoc DL = N->getDebugLoc();
|
|
SDValue BaseShAmt;
|
|
if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
|
|
unsigned NumElts = VT.getVectorNumElements();
|
|
unsigned i = 0;
|
|
for (; i != NumElts; ++i) {
|
|
SDValue Arg = ShAmtOp.getOperand(i);
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
BaseShAmt = Arg;
|
|
break;
|
|
}
|
|
for (; i != NumElts; ++i) {
|
|
SDValue Arg = ShAmtOp.getOperand(i);
|
|
if (Arg.getOpcode() == ISD::UNDEF) continue;
|
|
if (Arg != BaseShAmt) {
|
|
return SDValue();
|
|
}
|
|
}
|
|
} else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
|
|
cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
|
|
BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
|
|
DAG.getIntPtrConstant(0));
|
|
} else
|
|
return SDValue();
|
|
|
|
if (EltVT.bitsGT(MVT::i32))
|
|
BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
|
|
else if (EltVT.bitsLT(MVT::i32))
|
|
BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
|
|
|
|
// The shift amount is identical so we can do a vector shift.
|
|
SDValue ValOp = N->getOperand(0);
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
assert(0 && "Unknown shift opcode!");
|
|
break;
|
|
case ISD::SHL:
|
|
if (VT == MVT::v2i64)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
if (VT == MVT::v4i32)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
if (VT == MVT::v8i16)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
break;
|
|
case ISD::SRA:
|
|
if (VT == MVT::v4i32)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
if (VT == MVT::v8i16)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
break;
|
|
case ISD::SRL:
|
|
if (VT == MVT::v2i64)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
if (VT == MVT::v4i32)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
if (VT == MVT::v8i16)
|
|
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
|
|
DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
|
|
ValOp, BaseShAmt);
|
|
break;
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
/// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
|
|
static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
|
|
const X86Subtarget *Subtarget) {
|
|
// Turn load->store of MMX types into GPR load/stores. This avoids clobbering
|
|
// the FP state in cases where an emms may be missing.
|
|
// A preferable solution to the general problem is to figure out the right
|
|
// places to insert EMMS. This qualifies as a quick hack.
|
|
|
|
// Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
|
|
StoreSDNode *St = cast<StoreSDNode>(N);
|
|
MVT VT = St->getValue().getValueType();
|
|
if (VT.getSizeInBits() != 64)
|
|
return SDValue();
|
|
|
|
const Function *F = DAG.getMachineFunction().getFunction();
|
|
bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
|
|
bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
|
|
&& Subtarget->hasSSE2();
|
|
if ((VT.isVector() ||
|
|
(VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
|
|
isa<LoadSDNode>(St->getValue()) &&
|
|
!cast<LoadSDNode>(St->getValue())->isVolatile() &&
|
|
St->getChain().hasOneUse() && !St->isVolatile()) {
|
|
SDNode* LdVal = St->getValue().getNode();
|
|
LoadSDNode *Ld = 0;
|
|
int TokenFactorIndex = -1;
|
|
SmallVector<SDValue, 8> Ops;
|
|
SDNode* ChainVal = St->getChain().getNode();
|
|
// Must be a store of a load. We currently handle two cases: the load
|
|
// is a direct child, and it's under an intervening TokenFactor. It is
|
|
// possible to dig deeper under nested TokenFactors.
|
|
if (ChainVal == LdVal)
|
|
Ld = cast<LoadSDNode>(St->getChain());
|
|
else if (St->getValue().hasOneUse() &&
|
|
ChainVal->getOpcode() == ISD::TokenFactor) {
|
|
for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
|
|
if (ChainVal->getOperand(i).getNode() == LdVal) {
|
|
TokenFactorIndex = i;
|
|
Ld = cast<LoadSDNode>(St->getValue());
|
|
} else
|
|
Ops.push_back(ChainVal->getOperand(i));
|
|
}
|
|
}
|
|
|
|
if (!Ld || !ISD::isNormalLoad(Ld))
|
|
return SDValue();
|
|
|
|
// If this is not the MMX case, i.e. we are just turning i64 load/store
|
|
// into f64 load/store, avoid the transformation if there are multiple
|
|
// uses of the loaded value.
|
|
if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
|
|
return SDValue();
|
|
|
|
DebugLoc LdDL = Ld->getDebugLoc();
|
|
DebugLoc StDL = N->getDebugLoc();
|
|
// If we are a 64-bit capable x86, lower to a single movq load/store pair.
|
|
// Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
|
|
// pair instead.
|
|
if (Subtarget->is64Bit() || F64IsLegal) {
|
|
MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
|
|
SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
|
|
Ld->getBasePtr(), Ld->getSrcValue(),
|
|
Ld->getSrcValueOffset(), Ld->isVolatile(),
|
|
Ld->getAlignment());
|
|
SDValue NewChain = NewLd.getValue(1);
|
|
if (TokenFactorIndex != -1) {
|
|
Ops.push_back(NewChain);
|
|
NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
|
|
Ops.size());
|
|
}
|
|
return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
|
|
St->getSrcValue(), St->getSrcValueOffset(),
|
|
St->isVolatile(), St->getAlignment());
|
|
}
|
|
|
|
// Otherwise, lower to two pairs of 32-bit loads / stores.
|
|
SDValue LoAddr = Ld->getBasePtr();
|
|
SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
|
|
DAG.getConstant(4, MVT::i32));
|
|
|
|
SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
|
|
Ld->getSrcValue(), Ld->getSrcValueOffset(),
|
|
Ld->isVolatile(), Ld->getAlignment());
|
|
SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
|
|
Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
|
|
Ld->isVolatile(),
|
|
MinAlign(Ld->getAlignment(), 4));
|
|
|
|
SDValue NewChain = LoLd.getValue(1);
|
|
if (TokenFactorIndex != -1) {
|
|
Ops.push_back(LoLd);
|
|
Ops.push_back(HiLd);
|
|
NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
|
|
Ops.size());
|
|
}
|
|
|
|
LoAddr = St->getBasePtr();
|
|
HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
|
|
DAG.getConstant(4, MVT::i32));
|
|
|
|
SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
|
|
St->getSrcValue(), St->getSrcValueOffset(),
|
|
St->isVolatile(), St->getAlignment());
|
|
SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
|
|
St->getSrcValue(),
|
|
St->getSrcValueOffset() + 4,
|
|
St->isVolatile(),
|
|
MinAlign(St->getAlignment(), 4));
|
|
return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
|
|
/// X86ISD::FXOR nodes.
|
|
static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
|
|
assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
|
|
// F[X]OR(0.0, x) -> x
|
|
// F[X]OR(x, 0.0) -> x
|
|
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
|
|
if (C->getValueAPF().isPosZero())
|
|
return N->getOperand(1);
|
|
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
|
|
if (C->getValueAPF().isPosZero())
|
|
return N->getOperand(0);
|
|
return SDValue();
|
|
}
|
|
|
|
/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
|
|
static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
|
|
// FAND(0.0, x) -> 0.0
|
|
// FAND(x, 0.0) -> 0.0
|
|
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
|
|
if (C->getValueAPF().isPosZero())
|
|
return N->getOperand(0);
|
|
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
|
|
if (C->getValueAPF().isPosZero())
|
|
return N->getOperand(1);
|
|
return SDValue();
|
|
}
|
|
|
|
static SDValue PerformBTCombine(SDNode *N,
|
|
SelectionDAG &DAG,
|
|
TargetLowering::DAGCombinerInfo &DCI) {
|
|
// BT ignores high bits in the bit index operand.
|
|
SDValue Op1 = N->getOperand(1);
|
|
if (Op1.hasOneUse()) {
|
|
unsigned BitWidth = Op1.getValueSizeInBits();
|
|
APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
|
|
APInt KnownZero, KnownOne;
|
|
TargetLowering::TargetLoweringOpt TLO(DAG);
|
|
TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
|
if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
|
|
TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
|
|
DCI.CommitTargetLoweringOpt(TLO);
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
|
|
DAGCombinerInfo &DCI) const {
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
switch (N->getOpcode()) {
|
|
default: break;
|
|
case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
|
|
case ISD::BUILD_VECTOR:
|
|
return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
|
|
case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
|
|
case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
|
|
case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
|
|
case ISD::SHL:
|
|
case ISD::SRA:
|
|
case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
|
|
case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
|
|
case X86ISD::FXOR:
|
|
case X86ISD::FOR: return PerformFORCombine(N, DAG);
|
|
case X86ISD::FAND: return PerformFANDCombine(N, DAG);
|
|
case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
|
|
}
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Inline Assembly Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
X86TargetLowering::ConstraintType
|
|
X86TargetLowering::getConstraintType(const std::string &Constraint) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
case 'A':
|
|
return C_Register;
|
|
case 'f':
|
|
case 'r':
|
|
case 'R':
|
|
case 'l':
|
|
case 'q':
|
|
case 'Q':
|
|
case 'x':
|
|
case 'y':
|
|
case 'Y':
|
|
return C_RegisterClass;
|
|
case 'e':
|
|
case 'Z':
|
|
return C_Other;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
}
|
|
|
|
/// LowerXConstraint - try to replace an X constraint, which matches anything,
|
|
/// with another that has more specific requirements based on the type of the
|
|
/// corresponding operand.
|
|
const char *X86TargetLowering::
|
|
LowerXConstraint(MVT ConstraintVT) const {
|
|
// FP X constraints get lowered to SSE1/2 registers if available, otherwise
|
|
// 'f' like normal targets.
|
|
if (ConstraintVT.isFloatingPoint()) {
|
|
if (Subtarget->hasSSE2())
|
|
return "Y";
|
|
if (Subtarget->hasSSE1())
|
|
return "x";
|
|
}
|
|
|
|
return TargetLowering::LowerXConstraint(ConstraintVT);
|
|
}
|
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
/// vector. If it is invalid, don't add anything to Ops.
|
|
void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
|
char Constraint,
|
|
bool hasMemory,
|
|
std::vector<SDValue>&Ops,
|
|
SelectionDAG &DAG) const {
|
|
SDValue Result(0, 0);
|
|
|
|
switch (Constraint) {
|
|
default: break;
|
|
case 'I':
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
if (C->getZExtValue() <= 31) {
|
|
Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
|
|
break;
|
|
}
|
|
}
|
|
return;
|
|
case 'J':
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
if (C->getZExtValue() <= 63) {
|
|
Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
|
|
break;
|
|
}
|
|
}
|
|
return;
|
|
case 'N':
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
if (C->getZExtValue() <= 255) {
|
|
Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
|
|
break;
|
|
}
|
|
}
|
|
return;
|
|
case 'e': {
|
|
// 32-bit signed value
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
const ConstantInt *CI = C->getConstantIntValue();
|
|
if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
|
|
// Widen to 64 bits here to get it sign extended.
|
|
Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
|
|
break;
|
|
}
|
|
// FIXME gcc accepts some relocatable values here too, but only in certain
|
|
// memory models; it's complicated.
|
|
}
|
|
return;
|
|
}
|
|
case 'Z': {
|
|
// 32-bit unsigned value
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
const ConstantInt *CI = C->getConstantIntValue();
|
|
if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
|
|
Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
|
|
break;
|
|
}
|
|
}
|
|
// FIXME gcc accepts some relocatable values here too, but only in certain
|
|
// memory models; it's complicated.
|
|
return;
|
|
}
|
|
case 'i': {
|
|
// Literal immediates are always ok.
|
|
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
|
|
// Widen to 64 bits here to get it sign extended.
|
|
Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
|
|
break;
|
|
}
|
|
|
|
// If we are in non-pic codegen mode, we allow the address of a global (with
|
|
// an optional displacement) to be used with 'i'.
|
|
GlobalAddressSDNode *GA = 0;
|
|
int64_t Offset = 0;
|
|
|
|
// Match either (GA), (GA+C), (GA+C1+C2), etc.
|
|
while (1) {
|
|
if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
|
|
Offset += GA->getOffset();
|
|
break;
|
|
} else if (Op.getOpcode() == ISD::ADD) {
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
|
Offset += C->getZExtValue();
|
|
Op = Op.getOperand(0);
|
|
continue;
|
|
}
|
|
} else if (Op.getOpcode() == ISD::SUB) {
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
|
Offset += -C->getZExtValue();
|
|
Op = Op.getOperand(0);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
// Otherwise, this isn't something we can handle, reject it.
|
|
return;
|
|
}
|
|
|
|
if (hasMemory)
|
|
Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(), Offset, DAG);
|
|
else
|
|
Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
|
|
Offset);
|
|
Result = Op;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (Result.getNode()) {
|
|
Ops.push_back(Result);
|
|
return;
|
|
}
|
|
return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
|
|
Ops, DAG);
|
|
}
|
|
|
|
std::vector<unsigned> X86TargetLowering::
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT VT) const {
|
|
if (Constraint.size() == 1) {
|
|
// FIXME: not handling fp-stack yet!
|
|
switch (Constraint[0]) { // GCC X86 Constraint Letters
|
|
default: break; // Unknown constraint letter
|
|
case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
|
|
case 'Q': // Q_REGS
|
|
if (VT == MVT::i32)
|
|
return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
|
|
else if (VT == MVT::i16)
|
|
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
|
|
else if (VT == MVT::i8)
|
|
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
|
|
else if (VT == MVT::i64)
|
|
return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
}
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT VT) const {
|
|
// First, see if this is a constraint that directly corresponds to an LLVM
|
|
// register class.
|
|
if (Constraint.size() == 1) {
|
|
// GCC Constraint Letters
|
|
switch (Constraint[0]) {
|
|
default: break;
|
|
case 'r': // GENERAL_REGS
|
|
case 'R': // LEGACY_REGS
|
|
case 'l': // INDEX_REGS
|
|
if (VT == MVT::i8)
|
|
return std::make_pair(0U, X86::GR8RegisterClass);
|
|
if (VT == MVT::i16)
|
|
return std::make_pair(0U, X86::GR16RegisterClass);
|
|
if (VT == MVT::i32 || !Subtarget->is64Bit())
|
|
return std::make_pair(0U, X86::GR32RegisterClass);
|
|
return std::make_pair(0U, X86::GR64RegisterClass);
|
|
case 'f': // FP Stack registers.
|
|
// If SSE is enabled for this VT, use f80 to ensure the isel moves the
|
|
// value to the correct fpstack register class.
|
|
if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
|
|
return std::make_pair(0U, X86::RFP32RegisterClass);
|
|
if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
|
|
return std::make_pair(0U, X86::RFP64RegisterClass);
|
|
return std::make_pair(0U, X86::RFP80RegisterClass);
|
|
case 'y': // MMX_REGS if MMX allowed.
|
|
if (!Subtarget->hasMMX()) break;
|
|
return std::make_pair(0U, X86::VR64RegisterClass);
|
|
case 'Y': // SSE_REGS if SSE2 allowed
|
|
if (!Subtarget->hasSSE2()) break;
|
|
// FALL THROUGH.
|
|
case 'x': // SSE_REGS if SSE1 allowed
|
|
if (!Subtarget->hasSSE1()) break;
|
|
|
|
switch (VT.getSimpleVT()) {
|
|
default: break;
|
|
// Scalar SSE types.
|
|
case MVT::f32:
|
|
case MVT::i32:
|
|
return std::make_pair(0U, X86::FR32RegisterClass);
|
|
case MVT::f64:
|
|
case MVT::i64:
|
|
return std::make_pair(0U, X86::FR64RegisterClass);
|
|
// Vector types.
|
|
case MVT::v16i8:
|
|
case MVT::v8i16:
|
|
case MVT::v4i32:
|
|
case MVT::v2i64:
|
|
case MVT::v4f32:
|
|
case MVT::v2f64:
|
|
return std::make_pair(0U, X86::VR128RegisterClass);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Use the default implementation in TargetLowering to convert the register
|
|
// constraint into a member of a register class.
|
|
std::pair<unsigned, const TargetRegisterClass*> Res;
|
|
Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
// Not found as a standard register?
|
|
if (Res.second == 0) {
|
|
// GCC calls "st(0)" just plain "st".
|
|
if (StringsEqualNoCase("{st}", Constraint)) {
|
|
Res.first = X86::ST0;
|
|
Res.second = X86::RFP80RegisterClass;
|
|
}
|
|
// 'A' means EAX + EDX.
|
|
if (Constraint == "A") {
|
|
Res.first = X86::EAX;
|
|
Res.second = X86::GRADRegisterClass;
|
|
}
|
|
return Res;
|
|
}
|
|
|
|
// Otherwise, check to see if this is a register class of the wrong value
|
|
// type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
|
|
// turn into {ax},{dx}.
|
|
if (Res.second->hasType(VT))
|
|
return Res; // Correct type already, nothing to do.
|
|
|
|
// All of the single-register GCC register classes map their values onto
|
|
// 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
|
|
// really want an 8-bit or 32-bit register, map to the appropriate register
|
|
// class and return the appropriate register.
|
|
if (Res.second == X86::GR16RegisterClass) {
|
|
if (VT == MVT::i8) {
|
|
unsigned DestReg = 0;
|
|
switch (Res.first) {
|
|
default: break;
|
|
case X86::AX: DestReg = X86::AL; break;
|
|
case X86::DX: DestReg = X86::DL; break;
|
|
case X86::CX: DestReg = X86::CL; break;
|
|
case X86::BX: DestReg = X86::BL; break;
|
|
}
|
|
if (DestReg) {
|
|
Res.first = DestReg;
|
|
Res.second = X86::GR8RegisterClass;
|
|
}
|
|
} else if (VT == MVT::i32) {
|
|
unsigned DestReg = 0;
|
|
switch (Res.first) {
|
|
default: break;
|
|
case X86::AX: DestReg = X86::EAX; break;
|
|
case X86::DX: DestReg = X86::EDX; break;
|
|
case X86::CX: DestReg = X86::ECX; break;
|
|
case X86::BX: DestReg = X86::EBX; break;
|
|
case X86::SI: DestReg = X86::ESI; break;
|
|
case X86::DI: DestReg = X86::EDI; break;
|
|
case X86::BP: DestReg = X86::EBP; break;
|
|
case X86::SP: DestReg = X86::ESP; break;
|
|
}
|
|
if (DestReg) {
|
|
Res.first = DestReg;
|
|
Res.second = X86::GR32RegisterClass;
|
|
}
|
|
} else if (VT == MVT::i64) {
|
|
unsigned DestReg = 0;
|
|
switch (Res.first) {
|
|
default: break;
|
|
case X86::AX: DestReg = X86::RAX; break;
|
|
case X86::DX: DestReg = X86::RDX; break;
|
|
case X86::CX: DestReg = X86::RCX; break;
|
|
case X86::BX: DestReg = X86::RBX; break;
|
|
case X86::SI: DestReg = X86::RSI; break;
|
|
case X86::DI: DestReg = X86::RDI; break;
|
|
case X86::BP: DestReg = X86::RBP; break;
|
|
case X86::SP: DestReg = X86::RSP; break;
|
|
}
|
|
if (DestReg) {
|
|
Res.first = DestReg;
|
|
Res.second = X86::GR64RegisterClass;
|
|
}
|
|
}
|
|
} else if (Res.second == X86::FR32RegisterClass ||
|
|
Res.second == X86::FR64RegisterClass ||
|
|
Res.second == X86::VR128RegisterClass) {
|
|
// Handle references to XMM physical registers that got mapped into the
|
|
// wrong class. This can happen with constraints like {xmm0} where the
|
|
// target independent register mapper will just pick the first match it can
|
|
// find, ignoring the required type.
|
|
if (VT == MVT::f32)
|
|
Res.second = X86::FR32RegisterClass;
|
|
else if (VT == MVT::f64)
|
|
Res.second = X86::FR64RegisterClass;
|
|
else if (X86::VR128RegisterClass->hasType(VT))
|
|
Res.second = X86::VR128RegisterClass;
|
|
}
|
|
|
|
return Res;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Widen vector type
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getWidenVectorType: given a vector type, returns the type to widen
|
|
/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
|
|
/// If there is no vector type that we want to widen to, returns MVT::Other
|
|
/// When and where to widen is target dependent based on the cost of
|
|
/// scalarizing vs using the wider vector type.
|
|
|
|
MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
|
|
assert(VT.isVector());
|
|
if (isTypeLegal(VT))
|
|
return VT;
|
|
|
|
// TODO: In computeRegisterProperty, we can compute the list of legal vector
|
|
// type based on element type. This would speed up our search (though
|
|
// it may not be worth it since the size of the list is relatively
|
|
// small).
|
|
MVT EltVT = VT.getVectorElementType();
|
|
unsigned NElts = VT.getVectorNumElements();
|
|
|
|
// On X86, it make sense to widen any vector wider than 1
|
|
if (NElts <= 1)
|
|
return MVT::Other;
|
|
|
|
for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
|
|
nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
|
|
MVT SVT = (MVT::SimpleValueType)nVT;
|
|
|
|
if (isTypeLegal(SVT) &&
|
|
SVT.getVectorElementType() == EltVT &&
|
|
SVT.getVectorNumElements() > NElts)
|
|
return SVT;
|
|
}
|
|
return MVT::Other;
|
|
}
|