Evan Cheng 4d54e5b2dd Tail merging pass shall not break up IT blocks. rdar://8115404 ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8

2010-06-22 01:18:16 +00:00

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Mangler.h

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SubtargetFeature.h

The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a

2010-05-11 00:30:02 +00:00

Target.td

Remove isTwoAddress from llvm.

2010-06-21 20:35:09 +00:00

TargetAsmBackend.h

MC: Change RelaxInstruction to only take the input and output instructions.

2010-05-26 18:15:06 +00:00

TargetAsmLexer.h

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TargetAsmParser.h

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TargetCallingConv.td

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TargetData.h

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TargetELFWriterInfo.h

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TargetFrameInfo.h

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TargetInstrDesc.h

Start TargetRegisterClass indices at 0 instead of 1, so that

2010-06-18 18:13:55 +00:00

TargetInstrInfo.h

Tail merging pass shall not break up IT blocks. rdar://8115404

2010-06-22 01:18:16 +00:00

TargetInstrItineraries.h

declare a class with 'class' instead of struct to avoid tag mismatch

2010-06-12 15:46:56 +00:00

TargetIntrinsicInfo.h

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TargetJITInfo.h

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TargetLowering.h

Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,

2010-06-18 01:05:21 +00:00

TargetLoweringObjectFile.h

Add a new section and accessor for TLS data.

2010-05-22 00:00:58 +00:00

TargetMachine.h

MC: Add TargetMachine support for setting the value of MCRelaxAll with

2010-05-26 21:48:55 +00:00

TargetOpcodes.h

- Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it

2010-06-09 18:15:36 +00:00

TargetOptions.h

Remove the -enable-sjlj-eh option, which doesn't do anything.

2010-05-02 15:36:26 +00:00

TargetRegisterInfo.h

Start TargetRegisterClass indices at 0 instead of 1, so that

2010-06-18 18:13:55 +00:00

TargetRegistry.h

Currently, createMachOStreamer() is invoked directly in llvm-mc which

2010-05-21 12:54:43 +00:00

TargetSchedule.td

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TargetSelect.h

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TargetSelectionDAG.td

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TargetSelectionDAGInfo.h

Fix a comment.

2010-05-11 18:03:41 +00:00

TargetSubtarget.h

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