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A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174933 91177308-0d34-0410-b5e6-96231b3b80d8
371 lines
13 KiB
C++
371 lines
13 KiB
C++
//===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// ARM target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "armtti"
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/CostTable.h"
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using namespace llvm;
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// Declare the pass initialization routine locally as target-specific passes
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// don't havve a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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namespace llvm {
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void initializeARMTTIPass(PassRegistry &);
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}
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namespace {
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class ARMTTI : public ImmutablePass, public TargetTransformInfo {
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const ARMBaseTargetMachine *TM;
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const ARMSubtarget *ST;
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const ARMTargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
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public:
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ARMTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
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llvm_unreachable("This pass cannot be directly constructed");
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}
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ARMTTI(const ARMBaseTargetMachine *TM)
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: ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
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TLI(TM->getTargetLowering()) {
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initializeARMTTIPass(*PassRegistry::getPassRegistry());
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}
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virtual void initializePass() {
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pushTTIStack(this);
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}
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virtual void finalizePass() {
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popTTIStack();
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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TargetTransformInfo::getAnalysisUsage(AU);
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}
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/// Pass identification.
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static char ID;
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/// Provide necessary pointer adjustments for the two base classes.
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virtual void *getAdjustedAnalysisPointer(const void *ID) {
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if (ID == &TargetTransformInfo::ID)
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return (TargetTransformInfo*)this;
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return this;
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}
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/// \name Scalar TTI Implementations
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/// @{
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virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool Vector) const {
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if (Vector) {
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if (ST->hasNEON())
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return 16;
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return 0;
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}
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if (ST->isThumb1Only())
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return 8;
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return 16;
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}
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unsigned getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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if (ST->hasNEON())
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return 128;
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return 0;
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}
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return 32;
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}
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unsigned getMaximumUnrollFactor() const {
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// These are out of order CPUs:
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if (ST->isCortexA15() || ST->isSwift())
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return 2;
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return 1;
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}
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unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
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int Index, Type *SubTp) const;
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unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const;
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unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const;
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const;
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unsigned getAddressComputationCost(Type *Val) const;
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/// @}
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};
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} // end anonymous namespace
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INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
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"ARM Target Transform Info", true, true, false)
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char ARMTTI::ID = 0;
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ImmutablePass *
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llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
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return new ARMTTI(TM);
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}
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unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
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assert(Ty->isIntegerTy());
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unsigned Bits = Ty->getPrimitiveSizeInBits();
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if (Bits == 0 || Bits > 32)
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return 4;
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int32_t SImmVal = Imm.getSExtValue();
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uint32_t ZImmVal = Imm.getZExtValue();
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if (!ST->isThumb()) {
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if ((SImmVal >= 0 && SImmVal < 65536) ||
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(ARM_AM::getSOImmVal(ZImmVal) != -1) ||
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(ARM_AM::getSOImmVal(~ZImmVal) != -1))
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return 1;
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return ST->hasV6T2Ops() ? 2 : 3;
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} else if (ST->isThumb2()) {
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if ((SImmVal >= 0 && SImmVal < 65536) ||
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(ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
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(ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
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return 1;
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return ST->hasV6T2Ops() ? 2 : 3;
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} else /*Thumb1*/ {
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if (SImmVal >= 0 && SImmVal < 256)
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return 1;
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if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
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return 2;
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// Load from constantpool.
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return 3;
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}
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return 2;
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}
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unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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EVT SrcTy = TLI->getValueType(Src);
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EVT DstTy = TLI->getValueType(Dst);
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if (!SrcTy.isSimple() || !DstTy.isSimple())
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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// Some arithmetic, load and store operations have specific instructions
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// to cast up/down their types automatically at no extra cost.
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// TODO: Get these tables to know at least what the related operations are.
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static const TypeConversionCostTblEntry<MVT> NEONVectorConversionTbl[] = {
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{ ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
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{ ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
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{ ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
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{ ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
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{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
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{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
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// Vector float <-> i32 conversions.
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
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// Vector double <-> i32 conversions.
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }
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};
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if (SrcTy.isVector() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup<MVT>(NEONVectorConversionTbl,
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array_lengthof(NEONVectorConversionTbl),
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ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONVectorConversionTbl[Idx].Cost;
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}
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// Scalar float to integer conversions.
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static const TypeConversionCostTblEntry<MVT> NEONFloatConversionTbl[] = {
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{ ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
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{ ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
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{ ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
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{ ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
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};
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if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup<MVT>(NEONFloatConversionTbl,
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array_lengthof(NEONFloatConversionTbl),
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ISD, DstTy.getSimpleVT(),
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SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONFloatConversionTbl[Idx].Cost;
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}
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// Scalar integer to float conversions.
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static const TypeConversionCostTblEntry<MVT> NEONIntegerConversionTbl[] = {
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
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};
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if (SrcTy.isInteger() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup<MVT>(NEONIntegerConversionTbl,
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array_lengthof(NEONIntegerConversionTbl),
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ISD, DstTy.getSimpleVT(),
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SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONIntegerConversionTbl[Idx].Cost;
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}
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// Scalar integer conversion costs.
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static const TypeConversionCostTblEntry<MVT> ARMIntegerConversionTbl[] = {
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// i16 -> i64 requires two dependent operations.
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{ ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
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// Truncates on i64 are assumed to be free.
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{ ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
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};
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if (SrcTy.isInteger()) {
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int Idx =
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ConvertCostTableLookup<MVT>(ARMIntegerConversionTbl,
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array_lengthof(ARMIntegerConversionTbl),
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ISD, DstTy.getSimpleVT(),
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SrcTy.getSimpleVT());
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if (Idx != -1)
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return ARMIntegerConversionTbl[Idx].Cost;
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}
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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}
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unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy,
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unsigned Index) const {
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// Penalize inserting into an D-subregister. We end up with a three times
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// lower estimated throughput on swift.
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if (ST->isSwift() &&
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Opcode == Instruction::InsertElement &&
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ValTy->isVectorTy() &&
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ValTy->getScalarSizeInBits() <= 32)
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return 3;
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return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index);
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}
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unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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// On NEON a a vector select gets lowered to vbsl.
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if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
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return LT.first;
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}
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return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
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}
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unsigned ARMTTI::getAddressComputationCost(Type *Ty) const {
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// In many cases the address computation is not merged into the instruction
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// addressing mode.
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return 1;
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}
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unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) const {
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// We only handle costs of reverse shuffles for now.
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if (Kind != SK_Reverse)
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return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
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static const CostTblEntry<MVT> NEONShuffleTbl[] = {
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// Reverse shuffle cost one instruction if we are shuffling within a double
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// word (vrev) or two if we shuffle a quad word (vrev, vext).
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{ ISD::VECTOR_SHUFFLE, MVT::v2i32, 1 },
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{ ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 },
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{ ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 },
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{ ISD::VECTOR_SHUFFLE, MVT::v2f64, 1 },
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{ ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
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{ ISD::VECTOR_SHUFFLE, MVT::v4f32, 2 },
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{ ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 },
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{ ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 }
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};
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
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int Idx = CostTableLookup<MVT>(NEONShuffleTbl, array_lengthof(NEONShuffleTbl),
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ISD::VECTOR_SHUFFLE, LT.second);
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if (Idx == -1)
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return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
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return LT.first * NEONShuffleTbl[Idx].Cost;
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}
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